~vdupras/duskos

d04ddb213355773a93fbdb413de59edd7fec7ad9 — Virgil Dupras 8 days ago 42eb297
rpi: Making UART0 (barely) work

This is a straight rewrite of osdev's tutorial, I have no idea what I'm doing.
But it's working!
2 files changed, 55 insertions(+), 4 deletions(-)

M Makefile
M fs/xcomp/arm/rpi/kernel.fs
M Makefile => Makefile +4 -0
@@ 45,6 45,10 @@ rpi.img: dusk $(ALLSRCS)
	dd if=/dev/zero of=$@ bs=1K count=1
	./dusk < buildrpi.fs

.PHONY: rpirun
rpirun: rpi.img
	qemu-system-arm -M raspi1ap -serial stdio -display none -kernel rpi.img

.PHONY: run
run: dusk
	stty -icanon -echo min 0; ./dusk ; stty icanon echo

M fs/xcomp/arm/rpi/kernel.fs => fs/xcomp/arm/rpi/kernel.fs +51 -4
@@ 3,13 3,60 @@
\ For RPI model 1A
$20000000 const MMIO_BASE
$200000 const GPIO_BASE
$94 const GPPUD
$98 const GPPUDCLK0
$1000 const UART0_BASE
$00 const UART0_DR
$04 const UART0_RSRECR
$18 const UART0_FR
$20 const UART0_ILPR
$24 const UART0_IBRD
$28 const UART0_FBRD
$2c const UART0_LCRH
$30 const UART0_CR
$34 const UART0_IFLS
$38 const UART0_IMSC
$3c const UART0_RIS
$40 const UART0_MIS
$44 const UART0_ICR
$48 const UART0_DMACR
$80 const UART0_ITCR
$84 const UART0_ITIP
$88 const UART0_ITOP
$8c const UART0_TDR

$8000 to binstart
0 align4 here to org
r0 MMIO_BASE i) mov, \ r0 = MMIO_BASE
r0 r0 GPIO_BASE i) add, \ r0 = GPIO_BASE
r0 r0 UART0_BASE i) add, \ r0 = UART0_BASE
r1 'X' i) mov,
r0 r1 str,
$eafffff8 , \ hardcoded "b -8"
r2 r0 UART0_BASE i) add, \ r2 = UART0_BASE
\ Disable UART0
r3 r2 UART0_CR i) add, r1 0 i) mov, r1 r3 str,
\ Disable pull up/down for all GPIO pins & delay for 150 cycles.
r3 r0 GPPUD i) add, r1 0 i) mov, r1 r3 str,
\ TODO: add delay
\ Disable pull up/down for pin 14,15 & delay for 150 cycles.
r3 r0 GPPUDCLK0 i) add, r1 $c000 i) mov, r1 r3 str,
\ TODO: add delay
\ Write 0 to GPPUDCLK0 to make it take effect.
r3 r0 GPPUDCLK0 i) add, r1 0 i) mov, r1 r3 str,
\ Clear pending interrupts.
r3 r2 UART0_ICR i) add, r1 $700 i) mov, r1 r1 $ff i) add, r1 r3 str,
\ Set integer & fractional part of baud rate.
\ Divider = UART_CLOCK/(16 * Baud)
\ Fraction part register = (Fractional part * 64) + 0.5
\ Baud = 115200.
\ Divider = 3000000 / (16 * 115200) = 1.627 = ~1.
r3 r2 UART0_IBRD i) add, r1 1 i) mov, r1 r3 str,
\ Fractional part register = (.627 * 64) + 0.5 = 40.6 = ~40.
r3 r2 UART0_FBRD i) add, r1 40 i) mov, r1 r3 str,
\ Enable FIFO & 8 bit data transmission (1 stop bit, no parity).
r3 r2 UART0_LCRH i) add, r1 $70 i) mov, r1 r3 str,
\ Mask all interrupts.
r3 r2 UART0_IMSC i) add, r1 $700 i) mov, r1 r1 $f2 i) add, r1 r3 str,
\ Enable UART0, receive & transfer part of UART.
r3 r2 UART0_CR i) add, r1 $300 i) mov, r1 r1 $01 i) add, r1 r3 str,


r3 r2 UART0_DR i) add, r1 'X' i) mov, r1 r3 str,
$eafffffe , \ hardcoded "b -2"