~vdupras/collapseos

1ac7038863c9fb45f1d4414812dc33f3f1e04e6b — Virgil Dupras 14 days ago 74e211e
avra: add TOC and instructions list
6 files changed, 64 insertions(+), 21 deletions(-)

M blk/650
M blk/651
A blk/652
A blk/655
A blk/656
A blk/657
M blk/650 => blk/650 +3 -14
@@ 1,16 1,5 @@
AVR assembler

This assembler works very much like Z80 assembler (B200) so 
refer to this documentation first. Here, we document specifici-
ties.

All mnemonics in AVR have a single signature. Therefore, we     
don't need any "argtype" suffixes. 

Registers are referred to with consts R0-R31. There is
X, Y, Z, X+, Y+, Z+, X-, Y-, Z- for appropriate ops (LD, ST).
XL, XH, YL, YH, ZL, ZH are simple aliases to R26-R31.

Branching works differently. Instead of expecting a byte to be  
written after the naked op, branching words expect a displace-  
ment argument.                                           (cont.)
651 Guide                      655 Instructions list
660 Loader                     661-672 Code
672 Common AVR consts

M blk/651 => blk/651 +14 -7
@@ 1,9 1,16 @@
This is because there's bitwise ORing involved in the creation  
of the final opcode, which makes z80a's approach impractical.
This assembler works very much like Z80 assembler (B200) so
refer to this documentation first. Here, we document specifici-
ties.

This makes labelling a bit different too. Instead of expecting  
label words after the naked branching op, we rather have label
words expecting branching wordref as an argument. Examples:
All mnemonics in AVR have a single signature. Therefore, we
don't need any "argtype" suffixes.

L2 ' BRTS FLBL! ( branch forward to L2 )
L1 ' RJMP LBL, ( branch backward to L1 )
Registers are referred to with consts R0-R31. There is
X, Y, Z, X+, Y+, Z+, X-, Y-, Z- for appropriate ops (LD, ST).
XL, XH, YL, YH, ZL, ZH are simple aliases to R26-R31.

Branching works differently. Instead of expecting a byte to be
written after the naked op, branching words expect a displace-
ment argument.

                                                        (cont.)

A blk/652 => blk/652 +9 -0
@@ 0,0 1,9 @@
This is because there's bitwise ORing involved in the creation  
of the final opcode, which makes z80a's approach impractical.

This makes labelling a bit different too. Instead of expecting  
label words after the naked branching op, we rather have label
words expecting branching wordref as an argument. Examples:

L2 ' BRTS FLBL! ( branch forward to L2 )
L1 ' RJMP LBL, ( branch backward to L1 )

A blk/655 => blk/655 +16 -0
@@ 0,0 1,16 @@
AVR instructions list

OPRd (B663)
ASR  COM   DEC   INC   LAC   LAS   LAT   LSR   NEG   POP   PUSH
ROR  SWAP  XCH

OPRdRr (B664)
ADC  ADD   AND   CP    CPC   CPSE  EOR   MOV   MUL   OR   SBC
SUB

OPRdA (B664)
IN   OUT

OPRdK (B665)
ANDI CPI   LDI   ORI   SBCI   SBR   SUBI
                                                        (cont.)

A blk/656 => blk/656 +16 -0
@@ 0,0 1,16 @@
OPAb (B665)
CBI   SBI   SBIC  SBIS

OPNA (B666)
BREAK  CL[C,H,I,N,S,T,V,Z] SE[C,H,I,N,S,T,V,Z] EIJMP ICALL
EICALL IJMP  NOP   RET   RETI  SLEEP WDR

OPb (B667)
BCLR  BSET

OPRdb (B667)
BLD   BST   SBRC  SBRS

Special (B667,B670)
CLR   TST   LSL   LD    ST
                                                        (cont.)

A blk/657 => blk/657 +6 -0
@@ 0,0 1,6 @@
Flow (B668)
RJMP  RCALL
BR[BC,BS,CC,CS,EQ,NE,GE,HC,HS,ID,IE,LO,LT,MI,PL,SH,TC,TS,VC,VS]

Flow macros (B671)
LBL! LBL, SKIP, TO, FLBL, FLBL! BEGIN, AGAIN? AGAIN, IF, THEN,