Rig up I/O subsystem

I am not in love with this design

hdmg: print CPU state on SIGUSR1

hdmg: run CPU during update

hdmg: set fill to DMG dark green

hdmg: initial SDL riggings

dmg: add dmg struct

dmg::cart: initial commit

dmg: flesh out MMU

Not entirely satisfied with this

dmg: initial commit

sm83: implement interrupts

sm83: delay EI by one instruction

sm83: implement SET

sm83: implement RES

sm83: fix ALU flag resets

sm83: implement BIT

sm83: implement SWAP

sm83: don't abort on DAA

Most games will probably "work" with DAA stubbed out like this, so we
can finish it up later.

sm83: generate & stub out prefix instructions

sm83: implement variable cycle length

sm83: implement RST instructions