~sircmpwn/hdmg

91995c61a11b444952d194bcdca46391ce638d36 — Drew DeVault 1 year, 6 months ago cb46d25
sm83: implement variable cycle length
2 files changed, 52 insertions(+), 0 deletions(-)

M sm83/cpu.ha
M sm83/instr.ha
M sm83/cpu.ha => sm83/cpu.ha +4 -0
@@ 48,3 48,7 @@ export fn reset(cpu: *sm83) void = {
		...
	};
};

fn cycles(cpu: *sm83, n: int) void = {
	cpu.cycles -= n;
};

M sm83/instr.ha => sm83/instr.ha +48 -0
@@ 261,6 261,9 @@ fn exec_call_c_a16(cpu: *sm83) void = {
	if (cpu.regs.F & FL_C == FL_C) {
		push(cpu, cpu.regs.PC);
		cpu.regs.PC = addr;
		cycles(cpu, 24);
	} else {
		cycles(cpu, 12);
	};
};



@@ 269,6 272,9 @@ fn exec_call_nc_a16(cpu: *sm83) void = {
	if (cpu.regs.F & FL_C == 0) {
		push(cpu, cpu.regs.PC);
		cpu.regs.PC = addr;
		cycles(cpu, 24);
	} else {
		cycles(cpu, 12);
	};
};



@@ 277,6 283,9 @@ fn exec_call_z_a16(cpu: *sm83) void = {
	if (cpu.regs.F & FL_Z == FL_Z) {
		push(cpu, cpu.regs.PC);
		cpu.regs.PC = addr;
		cycles(cpu, 24);
	} else {
		cycles(cpu, 12);
	};
};



@@ 285,6 294,9 @@ fn exec_call_nz_a16(cpu: *sm83) void = {
	if (cpu.regs.F & FL_Z == 0) {
		push(cpu, cpu.regs.PC);
		cpu.regs.PC = addr;
		cycles(cpu, 24);
	} else {
		cycles(cpu, 12);
	};
};



@@ 301,6 313,9 @@ fn exec_ret_c(cpu: *sm83) void = {
	if (cpu.regs.F & FL_C == FL_C) {
		cpu.regs.PC = pop(cpu);
		cpu.int_ime = 1;
		cycles(cpu, 20);
	} else {
		cycles(cpu, 8);
	};
};



@@ 308,6 323,9 @@ fn exec_ret_nc(cpu: *sm83) void = {
	if (cpu.regs.F & FL_C == 0) {
		cpu.regs.PC = pop(cpu);
		cpu.int_ime = 1;
		cycles(cpu, 20);
	} else {
		cycles(cpu, 8);
	};
};



@@ 315,6 333,9 @@ fn exec_ret_z(cpu: *sm83) void = {
	if (cpu.regs.F & FL_Z == FL_Z) {
		cpu.regs.PC = pop(cpu);
		cpu.int_ime = 1;
		cycles(cpu, 20);
	} else {
		cycles(cpu, 8);
	};
};



@@ 322,6 343,9 @@ fn exec_ret_nz(cpu: *sm83) void = {
	if (cpu.regs.F & FL_Z == 0) {
		cpu.regs.PC = pop(cpu);
		cpu.int_ime = 1;
		cycles(cpu, 20);
	} else {
		cycles(cpu, 8);
	};
};



@@ 333,6 357,9 @@ fn exec_jp_c_a16(cpu: *sm83) void = {
	const addr = fetchd16(cpu);
	if (cpu.regs.F & FL_C == FL_C) {
		cpu.regs.PC = addr;
		cycles(cpu, 16);
	} else {
		cycles(cpu, 12);
	};
};



@@ 340,6 367,9 @@ fn exec_jp_nc_a16(cpu: *sm83) void = {
	const addr = fetchd16(cpu);
	if (cpu.regs.F & FL_C == 0) {
		cpu.regs.PC = addr;
		cycles(cpu, 16);
	} else {
		cycles(cpu, 12);
	};
};



@@ 347,6 377,9 @@ fn exec_jp_z_a16(cpu: *sm83) void = {
	const addr = fetchd16(cpu);
	if (cpu.regs.F & FL_Z == FL_Z) {
		cpu.regs.PC = addr;
		cycles(cpu, 16);
	} else {
		cycles(cpu, 12);
	};
};



@@ 354,6 387,9 @@ fn exec_jp_nz_a16(cpu: *sm83) void = {
	const addr = fetchd16(cpu);
	if (cpu.regs.F & FL_Z == 0) {
		cpu.regs.PC = addr;
		cycles(cpu, 16);
	} else {
		cycles(cpu, 12);
	};
};



@@ 371,6 407,9 @@ fn exec_jr_c_r8(cpu: *sm83) void = {
	const offs = fetchd8(cpu);
	if (cpu.regs.F & FL_C == FL_C) {
		jr(cpu, offs);
		cycles(cpu, 12);
	} else {
		cycles(cpu, 7);
	};
};



@@ 378,6 417,9 @@ fn exec_jr_nc_r8(cpu: *sm83) void = {
	const offs = fetchd8(cpu);
	if (cpu.regs.F & FL_C == 0) {
		jr(cpu, offs);
		cycles(cpu, 12);
	} else {
		cycles(cpu, 7);
	};
};



@@ 385,6 427,9 @@ fn exec_jr_z_r8(cpu: *sm83) void = {
	const offs = fetchd8(cpu);
	if (cpu.regs.F & FL_Z == FL_Z) {
		jr(cpu, offs);
		cycles(cpu, 12);
	} else {
		cycles(cpu, 7);
	};
};



@@ 392,6 437,9 @@ fn exec_jr_nz_r8(cpu: *sm83) void = {
	const offs = fetchd8(cpu);
	if (cpu.regs.F & FL_Z == 0) {
		jr(cpu, offs);
		cycles(cpu, 12);
	} else {
		cycles(cpu, 7);
	};
};