from migen import *
from migen.build.generic_platform import *
from migen.build.platforms import papilio_pro
from migen.genlib.fifo import SyncFIFO, SyncFIFOBuffered

import uart

class Echo(Module):
    def __init__(self, serial_pads, clk_period_ns, baud_rate):
        self.submodules.uart = uart.RS232PHY(serial_pads, clk_period_ns, baud_rate)
        self.submodules.fifo = SyncFIFOBuffered(8, 8)

        ###

        self.comb += [
            self.fifo.din.eq(self.uart.rx.data),
            self.fifo.we.eq(self.uart.rx.valid),

            self.uart.tx.data.eq(self.fifo.dout),
            self.fifo.re.eq(self.uart.tx.ready),
            self.uart.tx.valid.eq(self.fifo.readable),
        ]

if __name__ == '__main__':
    import sys
    if sys.argv[1] == 'build':
        plat = papilio_pro.Platform()

        led = plat.request("user_led")
        m = Module()
        m.submodules.echo = Echo(plat.request('serial'), plat.default_clk_period, baud_rate=2000000)

        plat.build(m)

    elif sys.argv[1] in 'test':
        data = [0xfa, 0x12, 0x66, 0x00]
        def tx(dut):
            for b in data:
                print('tx ' + hex(b))
                yield dut.loopback.tx.data.eq(b)
                yield dut.loopback.tx.valid.eq(1)
                yield
                yield dut.loopback.tx.valid.eq(0)

                while (yield dut.loopback.tx.ready) == 0:
                    yield

        def rx(dut):
            for b in data:
                while (yield dut.loopback.rx.valid) == 0:
                    yield

                v = (yield dut.loopback.rx.data)
                print('rx: ' + hex(v))
                assert v == b, hex(v)

                while (yield dut.loopback.rx.valid) == 1:
                    yield

        class DUT(Module):
            def __init__(self):
                self.serial_pads = Record([('tx', 1), ('rx', 1)])
                self.loop_serial_pads = Record([('tx', 1), ('rx', 1)])

                self.submodules.echo = Echo(self.serial_pads, 31.25, baud_rate=2000000)
                self.submodules.loopback = uart.RS232PHY(self.loop_serial_pads, 31.25, baud_rate=2000000)

                self.comb += [
                    self.serial_pads.rx.eq(self.loop_serial_pads.tx),
                    self.loop_serial_pads.rx.eq(self.serial_pads.tx)
                ]

        dut = DUT()
        run_simulation(dut, [rx(dut), tx(dut)], vcd_name='out.vcd')