~shiny/gbcap

f46ff179a3d21e812e868c344e0e3156ab20c118 — Thomas Spurden 3 months ago a25dd09 main
Fix readme formatting
1 files changed, 14 insertions(+), 14 deletions(-)

M README.md
M README.md => README.md +14 -14
@@ 1,5 1,5 @@
This is a hardware design to capture the LCD output of a Gameboy by connecting
an FPGA to some of the pins on the ribbon cable between the main and LCD board
an FPGA to some of the pins on the ribbon cable between the main and LCD boards
of a Gameboy.

# Quickstart


@@ 10,9 10,9 @@ Make sure you've got the `papilio-prog` bitfile loader from [here](http://papili

If using a [Papilio Pro] board

   ./run gbcap build
   ./papilio-prog/papilio-prog -f build/top.bit
   ./recv.py -b 2000000 /dev/ttyUSB1 -o frames
     ./run gbcap build
     ./papilio-prog/papilio-prog -f build/top.bit
     ./recv.py -b 2000000 /dev/ttyUSB1 -o frames

[papilio pro]: http://papilio.cc/index.php?n=Papilio.PapilioPro 



@@ 21,19 21,19 @@ If using a [Papilio Pro] board
This code (in `gbcap.py`) sets up which pins on the FPGA are expected to be
connected to which pins on the Gameboy:

  plat.add_extension([
      ('gb_lcd', 0,
          Subsignal('vsync', Pins('B:5')),
          Subsignal('hsync', Pins('B:4')),
          Subsignal('cpl', Pins('B:6')),
          Subsignal('clk', Pins('B:2')),
          Subsignal('pixel', Pins('B:0', 'B:1')))])
    plat.add_extension([
        ('gb_lcd', 0,
            Subsignal('vsync', Pins('B:5')),
            Subsignal('hsync', Pins('B:4')),
            Subsignal('cpl', Pins('B:6')),
            Subsignal('clk', Pins('B:2')),
            Subsignal('pixel', Pins('B:0', 'B:1')))])

# UART testing

   ./run uart_echo build
   ./papilio-prog/papilio-prog -f build/top.bit
   ./com.py -b 2000000 /dev/ttyUSB1 abcde
     ./run uart_echo build
     ./papilio-prog/papilio-prog -f build/top.bit
     ./com.py -b 2000000 /dev/ttyUSB1 abcde

Should output the second argument 'abcde' in the example back. If it doesn't
then something is wrong!