@@ 301,8 301,8 @@ if __name__ == '__main__':
with open(path, 'w') as f:
f.write(cvt.main_source)
- def verilate(files, output=None):
- cmd = ['verilator', '-Wno-COMBDLY', '-Wno-fatal', '-cc', '-CFLAGS', '-ggdb', '--trace', '--exe', '--build']
+ def verilate(files, extra_args, output=None):
+ cmd = ['verilator', '-Wno-COMBDLY', '-Wno-fatal', '-cc', '-CFLAGS', '-ggdb', '--exe', '--build'] + extra_args
if output is not None:
cmd += ['-o', output]
cmd += files
@@ 333,4 333,4 @@ if __name__ == '__main__':
}
c = convert(tb, ios=ios)
update_verilog_if_changed('gbcap_tb.v', c)
- verilate(['gbcap_tb.v', 'gbcap_tb_wrap.cpp'], output='gbcap_tb')
+ verilate(['gbcap_tb.v', 'gbcap_tb_wrap.cpp'], sys.argv[2:], output='gbcap_tb')
@@ 25,11 25,13 @@ int main(int argc, char **argv)
Verilated::commandArgs(argc, argv);
Vgbcap_tb* top = new Vgbcap_tb;
+#if VM_TRACE
Verilated::traceEverOn(true);
VerilatedVcdC* trace = new VerilatedVcdC;
top->trace(trace, 99);
trace->open("gbcap_tb.vcd");
+#endif
top->sys_rst = 1;
for(unsigned i = 0; i != 10; i += 1) {
@@ 71,11 73,15 @@ int main(int argc, char **argv)
/* Falling edge */
top->sys_clk = 0;
top->eval();
+#if VM_TRACE
trace->dump(sys_clk << 1);
+#endif
/* Rising edge */
top->sys_clk = 1;
top->eval();
+#if VM_TRACE
trace->dump((sys_clk << 1) + 1);
+#endif
if(top->line_pads_valid) {
top->line_pads_valid = 0;
@@ 103,7 109,9 @@ int main(int argc, char **argv)
sys_clk += 1;
}
+#if VM_TRACE
trace->close();
+#endif
delete top;
}
@@ 6,7 6,7 @@ if test $# -lt 2; then
fi
module=$1
-cmd=$2
+shift
# I installed Xilinx ISE in a VM and copied the resulting install here
XILINX_HOME=$HOME/xilinx-ise-home
@@ 15,4 15,4 @@ export XILINXD_LICENSE_FILE=$XILINX_HOME/.Xilinx/Xilinx.lic
export PYTHONPATH=$(pwd)/migen
-python3 "$module.py" "$cmd"
+python3 "$module.py" "$@"