~raitobezarius/sakaido

5babf90e7437df0244d415e610f76975a7ea8686 — Raito Bezarius 1 year, 7 months ago
initial commit: README
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# Sakaido: The Brillant Microprocessor

This project (will) use:

- Haskell for my personal netlist simulator ;
- Verilog for the HDL ;
- RISC-V RV32I ^[Though, RV64I is considered.] as a target ISA ;
- Icarus Verilog for simulation ;
- Papilio Duo as the FPGA development board ;
- Nix as a package manager

It is licensed under MIT license.