initial commit: README
1 files changed, 12 insertions(+), 0 deletions(-) A README.md
A => README.md
@@ 1,12 @@ # Sakaido: The Brillant Microprocessor This project (will) use: - Haskell for my personal netlist simulator ; - Verilog for the HDL ; - RISC-V RV32I ^[Though, RV64I is considered.] as a target ISA ; - Icarus Verilog for simulation ; - Papilio Duo as the FPGA development board ; - Nix as a package manager It is licensed under MIT license.