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A README.md

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+# Sakaido: The Brillant Microprocessor
+
+This project (will) use:
+
+- Haskell for my personal netlist simulator ;
+- Verilog for the HDL ;
+- RISC-V RV32I ^[Though, RV64I is considered.] as a target ISA ;
+- Icarus Verilog for simulation ;
+- Papilio Duo as the FPGA development board ;
+- Nix as a package manager
+
+It is licensed under MIT license.