~poptart/riscv-business

ad0ac9357fb922cd86059746dd7c267651cab7c3 — terrorbyte 2 years ago 818de68
Cleaned up a mistake about PC vs SP. Added example cpuinfo
2 files changed, 22 insertions(+), 1 deletions(-)

A doc/cpuinfo.txt
M src/asm1.s
A doc/cpuinfo.txt => doc/cpuinfo.txt +21 -0
@@ 0,0 1,21 @@
[root@fedora-riscv ~]# cat /proc/cpuinfo 
processor	: 0
hart		: 3
isa		: rv64imafdcu
mmu		: sv48

processor	: 1
hart		: 0
isa		: rv64imafdcu
mmu		: sv48

processor	: 2
hart		: 1
isa		: rv64imafdcu
mmu		: sv48

processor	: 3
hart		: 2
isa		: rv64imafdcu
mmu		: sv48


M src/asm1.s => src/asm1.s +1 -1
@@ 11,7 11,7 @@ _start:
	#
	# https://github.com/riscv/riscv-isa-manual/releases/download/draft-20190309-ceb9d83/riscv-spec.pdf 
	#
	# There are 32 registers (and a stack pointer) and contain 4
	# There are 32 registers (and a program counter) and contain 4
	# core instruction formats (refered to as R, I, S, and U-type)
	# and 2 "immediate" instruction formats (B, J-type). The types 
	# of registers determine the format of the instructions, which