~pixelherodev/zyg

ref: 7dccbd7d9dc502f2cd859c4c7ebd84a0d8f3acd7 zyg/test/rk9/8.zig -rw-r--r-- 1.6 KiB
7dccbd7dNoam Preil merge 6 months ago
                                                                                
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const SoC = RK.RK3328;

const RK = struct{
	const RK3328 = struct{
		const CPU = ARM.A53;
		const UART : type = struct {
			base: u32,
			const Registers = struct {
				// Receive buffer register
				const RBR = 0;
				// Transmit holding register
				const THR = 0;
				// Divisor latch (low)
				const DLL = 0b0;
				// Divisor latch (high)
				const DLH = 4;
				const LCR = 0xc;
			};
			const define = fn(base: u32) @This(){
				return @This(){
					.base = base,
				};
			};
		};
		const Peripherals = struct {
			const UART0 = UART.define(0xFF110000);
	//		const UART1 = 0xFF120000;
	//		const UART2 = 0xFF130000;
		};
	};
	const panic = fn() noreturn{
		//TODO: add a hlt in here and reduce power
		while(true){}
	};
};

const ARM = struct{
	const SpecialRegister = enum{
		const CPUACTLR_EL1 = "CPUACTLR_EL1";
		const set = fn(comptime reg: []const u8, val: u32) callconv(.Inline) void{
			// asm syntax rules:
			// $*N embeds COMPTIME string from argument N
			// $N references an argument which MUST be a LOCAL.
			asm("msr $2, $*1", reg, val);
		};
		const get = fn(comptime reg: []const u8) callconv(.Inline) u32 {
			return asm("mrs $*1, $>2", reg, u32);
		};
	};
	const A53 = struct {
		const Erratum = struct{
			const E855873 = fn() callconv(.Inline) void{
				var ACLTR = SpecialRegister.get(SpecialRegister.CPUACTLR_EL1);
				ACLTR = ACLTR | 1 << 44;
				SpecialRegister.set(SpecialRegister.CPUACTLR_EL1, ACLTR);
			};
			const all = fn() callconv(.Inline) void{
				E855873();
			};
		};
	};
};

pub export const start = fn() noreturn{
	defer RK.panic();
	SoC.CPU.Erratum.all();
	const UART = SoC.Peripherals.UART0;
};