~pixelherodev/spu-ii

7c070ed8c199863b71f39056c32aadfb2ff5e715 — Noam Preil 4 months ago 6d5b82b master
Fix tests with block sizes [2..5]
3 files changed, 41 insertions(+), 26 deletions(-)

M src/interpreter.zig
M src/test.zig
M src/translator.zig
M src/interpreter.zig => src/interpreter.zig +4 -0
@@ 173,6 173,10 @@ pub fn ExecuteBlock(self: *@This(), comptime size: ?u32) !void {
                },
            };

            if (instruction.command == .undefined0) {
                return;
            }

            switch (instruction.output) {
                .discard => {},
                .push => {

M src/test.zig => src/test.zig +16 -13
@@ 52,6 52,7 @@ fn hex_test(comptime x64: bool, comptime step_size: u32, comptime target: u16, c
        .buffer_size = 32 * 1024,
        .bus = &jit_bus,
    });
    recompiler.translator.absolute_end = target;
    defer recompiler.deinit();
    var interp = try interpreter.init(.{
        .buffer_size = 32 * 1024,


@@ 87,6 88,8 @@ fn hex_test(comptime x64: bool, comptime step_size: u32, comptime target: u16, c
        errdefer {
            if (step_size == 1) {
                std.debug.print("insn: {} @ 0x{x:0<4}\nlast: {} @ 0x{x:0<4}\n", .{ inst, current_pc, last_inst, last_pc });
            } else {
                std.debug.print("Block base: 0x{x:0<4}\n", .{current_pc});
            }
        }
        // Recompiler goes first, because it prints insn info at translation time instead of execution,


@@ 214,6 217,19 @@ test "3.hex, 32-bit alloc, step size 1" {
    }, "test/3.hex");
}

test "1.hex, 32-bit allocator, interpreter comparison, step size 10" {
    try hex_test(false, 10, 0x0056, null, struct {
        fn init(recompiler: *dynarec, interp: *interpreter) !void {
            interp.bus.muted = true;
            interp.bus.test_state.hide_exclamations = true;
            recompiler.bus.test_state.hide_exclamations = true;
        }
        fn callback(recompiler: *dynarec, interp: *interpreter) !void {
            std.debug.print("\n", .{});
        }
    }, "test/1.hex");
}

test "1.hex, 32-bit alloc, variable step size" {
    comptime var i: u32 = 1;
    inline while (i < 10) : (i += 1) {


@@ 230,16 246,3 @@ test "1.hex, 32-bit alloc, variable step size" {
        }, "test/1.hex");
    }
}

//test "1.hex, 32-bit allocator, interpreter comparison, step size 10" {
//    try hex_test(false, 10, 0x0056, null, struct {
//        fn init(recompiler: *dynarec, interp: *interpreter) !void {
//            interp.bus.muted = true;
//            interp.bus.test_state.hide_exclamations = true;
//            recompiler.bus.test_state.hide_exclamations = true;
//        }
//        fn callback(recompiler: *dynarec, interp: *interpreter) !void {
//            std.debug.print("\n", .{});
//        }
//    }, "test/1.hex");
//}

M src/translator.zig => src/translator.zig +21 -13
@@ 12,6 12,7 @@ const Reference = thor.Reference;

jit: *thor,
parent: *dynarec,
absolute_end: ?u16,

pub fn init(parent: *dynarec, buffer_size: usize) !@This() {
    var self = @This(){


@@ 20,6 21,7 @@ pub fn init(parent: *dynarec, buffer_size: usize) !@This() {
            .buffer_size = buffer_size,
            .allocator = parent.allocator,
        }),
        .absolute_end = null,
    };
    try self.jit.reserveInstructionBlocks(1);
    try self.jit.beginCode("exit").reserve(1);


@@ 221,6 223,12 @@ pub fn translate(self: *@This(), address: u16, len: ?u32) !fn () callconv(.C) vo
    while (len == null or count < len.?) {
        count += 1;
        self.invokeLog(0, 4);

        if (self.absolute_end) |a| {
            if (addr == a) {
                break;
            }
        }
        var instruction: CPU.Instruction = try self.parent.bus.read(CPU.Instruction, addr);

        while (@bitCast(u16, instruction) == 0) {


@@ 610,19 618,19 @@ pub fn translate(self: *@This(), address: u16, len: ?u32) !fn () callconv(.C) vo
                try self.jit.andr(reg, reg, treg2);
            },
            .jump => {
                //     if (instruction.command == .copy and instruction.input0 == .immediate) {
                //         // Absolute jump
                //         addr = try self.parent.bus.read(u16, base + 2);
                //     } else {
                self.jit.add(pc, output, .x0);
                const tmp = try regalloc.allocate();
                defer regalloc.relinquish(tmp, false);
                const treg = @intToEnum(Register, tmp);
                self.jit.LoadRegister(treg, 0xFFFF);
                try self.jit.andr(pc, pc, treg);
                branched = true;
                break;
                //   }
                if (instruction.command == .copy and instruction.input0 == .immediate) {
                    // Absolute jump
                    addr = try self.parent.bus.read(u16, base + 2);
                } else {
                    self.jit.add(pc, output, .x0);
                    const tmp = try regalloc.allocate();
                    defer regalloc.relinquish(tmp, false);
                    const treg = @intToEnum(Register, tmp);
                    self.jit.LoadRegister(treg, 0xFFFF);
                    try self.jit.andr(pc, pc, treg);
                    branched = true;
                    break;
                }
            },
            else => |c| {
                std.debug.warn("\x1b[31mUnimplemented output mode: {}\x1b[0m\n", .{c});