~omasanori/coreboot

c69ea328 — Jakub Czapiga 6 months ago master
libpayload: Add mock assert support for unit testing purposes

Some unit tests might require catching assert failures. This patch adds
an assert() variant depending on __TEST__ define passed to unit tests.

Change-Id: I7e4620400f27dbebc57c71bbf2bf9144ca65807f
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
16208307 — Jakub Czapiga 6 months ago
libpayload/tests: remove tests/include/mocks include path

Some files in tests/include/mocks might have the same name as main
libpayload include files. Remove this path from default includes to
force addition of mocks/ prefix in include paths. This will help
avoiding name clashes and will also make mock headers visible.

Change-Id: I4baa07472f0379d56423cf7152b1ecc9a4824539
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
72628fa8 — Evgeny Zinoviev 6 months ago
mb/lenovo: Enable MEI on Sandy Bridge ThinkPads

It was already enabled on T520 and L520, but disabled on X220, T420 and
T420s.

On X220, it was disabled by commit 0793afe9 (mb/lenovo/x220: disable ME).
I can't reproduce those issues today on linux 4.4 and linux 5.13.

Also, it breaks the me_disable feature, we already have a Kconfig option
to hide MEI in case of errors, and it will be hidden on disabled,
recovery, firmware update paths anyway.

Change-Id: I8e6d067a9c728443d00df541ac7a9a878df58b6a
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
b207f3f3 — Angel Pons 6 months ago
mb/prodrive/hermes: Number Ethernet devices

The Prodrive Hermes mainboard has four i211 Ethernet NICs and an i210
Ethernet NIC, but their numbering isn't consistent with the PCIe root
port function numbers. With only a M.2 SSD plugged in, Linux uses the
following names:

 PHY 0 ---> enp6s0
 PHY 1 ---> enp4s0
 PHY 2 ---> enp3s0
 PHY 3 ---> enp1s0
 PHY 4 ---> enp2s0

These names change after adding or removing PCIe devices in slots
connected to root ports that get enumerated before the NICs' root
ports, because the assignment of secondary bus numbers depends on
the enumeration order. Because of this, the "predictable" network
interface names are not at all predictable, which is awful.

To avoid this, describe the NICs using SMBIOS Type41 entries with the
correct instance numbers. With this patch, Linux uses these names:

 PHY 0 ---> eno0
 PHY 1 ---> eno1
 PHY 2 ---> eno2
 PHY 3 ---> eno3
 PHY 4 ---> eno4

No matter what PCIe devices are present, these names don't change.

Change-Id: I7a527298f84172f9135006083ad7e748dcc27911
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58628
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
8ebea127 — Michał Żygowski 6 months ago
mb/dell/optiplex_9010/devicetree.cb: Enable missing GPEs

Enable PCI_EXP_EN, PME_EN and PME_B0_EN GPEs used for PCI devices.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I4480921a294f35a0dfe1e5acd90d55f6fb4c85b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
aa133e42 — Michał Żygowski 6 months ago
mb/dell/optiplex_9010/Kconfig: Select Super I/O UART availability

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie1b270d49660fd60b6a91194167467c4453e1b6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
34b70fd1 — Tim Crawford 6 months ago
mb/system76/*: Enable dGPU temp/fan reporting

Select the EC option on boards with dGPUs to report GPU temperature and
fan data.

Tested on system76/oryp6. The GPU fan speed is reported in sensors when
the system is under load.

    system76_acpi-acpi-0
    Adapter: ACPI interface
    CPU fan:     1985 RPM
    GPU fan:     2348 RPM
    CPU temp:     +68.0°C
    GPU temp:      +0.0°C

Change-Id: Ieb45dc277c7eb11be1c50b9a9e3e20e3a88578b7
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
924c33b7 — Jeremy Soller 6 months ago
ec/system76/ec: acpi: Add dGPU thermal reporting

Add a new config for boards with dGPUs to enable reporting fan duty and
temperature. The dGPU is not yet enabled on any boards, so it always
reports the temp as 0. However, the EC firmware does use the dGPU's fan
and so reports valid information for fan speed.

Change-Id: Iae1063ee6a082a77ed026178eb9471bbc2b2fadf
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
12a98ffb — Tim Crawford 6 months ago
mb/system76/*: Disable IME by CMOS option

Add CMOS option to set IME mode. Default to "Disable" for CNL and TGL-H,
and "Enable" for TGL-U. Not set for KBL, which uses ME_CLEANER.

The HECI device must be enabled in devicetree for switching modes to
function correctly.

Change-Id: I3163dcb0a4af020c2cf6f94f2bb26380f17c253e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
3c01123a — Kane Chen 6 months ago
soc/intel/alderlake: remove tmp bar assignment for cpu crashlog

When the cpu_cl_discovery is called, coreboot actually assigns a BAR
to cpu crashlog pci device. Hence, we don't need to assign a tmp BAR
for cpu crashlog pci device

BUG=b:195327879
TEST=Found BERT table is created and the tcss function is ok in depthcharge

Change-Id: Ib7e6772be51ec4f26ef31fed6cb2bddef8ffc6be
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
d88d2da8 — Wisley Chen 6 months ago
mb/google/brya/var/redrix: Disable autonomous GPIO power management

With cr50 fw 0.3.22 or older version, it needs to disable autonomous
GPIO power management and then can update cr50 fw successfully.

BUG=b:202246591
TEST=FW_NAME=redrix emerge-brya coreboot chromeos-bootimage.

Change-Id: Idc01ebb4d3ef990f24f18bef5424b7d6ba683d49
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
15235b2d — Julian Stecklina 6 months ago
emulation/qemu-i440fx,q35: avoid writing to ROM

libcbfs has a workaround to avoid writing to ROM areas:

        /* Hacky way to not load programs over read only media. The stages
         * that would hit this path initialize themselves. */
        if ((ENV_BOOTBLOCK || ENV_SEPARATE_VERSTAGE) &&
            !CONFIG(NO_XIP_EARLY_STAGES) && CONFIG(BOOT_DEVICE_MEMORY_MAPPED)) {

This workaround is not triggered in QEMU, because
BOOT_DEVICE_MEMORY_MAPPED is only selected for SPI boot devices. This
results in confusing (to the VMM developer) writes to read-only
memory.

As far as I can tell, this issue is weird but harmless, because the
code does memcpy to ROM with source == destination. The concensus in
the mailing list thread [1] was that it's worthwhile to be fixed
regardless.

[1] https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/message/KDI6YQCPXSQF4NDUAAC7TIXQKSZ6T4X7/

Change-Id: I5cefbc31f917021236105f7dc969118d612ac399
Signed-off-by: Julian Stecklina <julian.stecklina@cyberus-technology.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
f1dbd673 — Sheng-Liang Pan 6 months ago
mb/google/trogdor: change pin define for quackingstick

change TP_EN pin to GPIO_67 for quackingstick

BUG=b:206862167
BRANCH=trogdor
TEST=make

Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I7cc1083111f46cd3489cbbb9e579c34dc972b0b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Bob Moragues <moragues@google.com>
e987845f — Ben Chuang 6 months ago
drivers/genesyslogic/gl9750: Add driver for Genesys Logic GL9750

The device is a PCIe Gen1 to SD 3.0 card reader controller to be
used in the Chromebook. The datasheet name is GL9750S and the revision
is 01.

The patch disables ASPM L0s.

BUG=b:206014046
TEST=Verify GL9750 enters L1 by observing CLKREQ# de-asserts.

Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Change-Id: I6d60cef41baade7457a159d3ce2f8d2e6b66e71c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
ea6a93f1 — Martin Roth 6 months ago
Makefiles: Hide skipping submodule info unless V=1

Currently, git prints out the submodules that are being skipped twice
on many builds.  This patch hides that output unless the build is set
to show it with `make V=1`.  This is the normal way of showing the extra
information during the build.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I7b5c7f1f79dcc88793a9a21f2e92e7accc5de1e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59511
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1d565b50 — Raul E Rangel 6 months ago
cpu/intel/hyperthreading: Add missing header <arch/cpu.h>

This file is using cpuid_result and cpuid(). I also removed the spinlock
header since it's not used. This is what was previously providing the
cpu.h header.

BUG=b:179699789
TEST=none

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Idc3daa64562c4a4d57b678f13726509b480ba050
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
5e3c454f — Rob Barnes 6 months ago
drivers/tpm: Add firmware-power-managed DSD property

Introduce firmware-power-managed DSD ACPI property for TPM devices.
This property can be checked by the kernel TPM driver to override how
the TPM power states are managed. This is a tri-state flag, true,
false, or unset. So an enum used to keep the flag is unset by default.

When firmware-power-managed is true, the kernel driver will not send a
shutdown during s2idle/s0i3 suspend.

BUG=b:200578885
BRANCH=None
TEST=TPM shutdown is triggered on s0ix suspend on guybrush with patched
kernel

Change-Id: Ia48ead856fc0c6e637a2e07a5ecc58423f599c5b
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
b35acf92 — Rob Barnes 6 months ago
soc/amd/psp_verstage: Init TPM on S0i3 resume

Add option to initialize the TPM in PSP verstage during s0i3 resume.
This is needed if the TPM is reset in s0i3. FSDL is handling
restoring everything else, so only the minimum TPM initialization is done.
Move aoac and i2c init before psp_verstrage_s0i3_resume becasue i2c
needs to be ready before attempting to restore tpm.

BUG=b:200578885,b:197965075
TEST=Multiple cycles of S0i3 suspend resume. ~66ms of additional delay.
BRANCH=None

Change-Id: Ie511928da6a8b4be62621fd2c4c31a8d1e724d48
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2c89d08d — Patrick Georgi 6 months ago
Documentation: Add warning about "private" changes on Gerrit

Private changes on Gerrit are a tricky beast in that they're well hidden
in the UI and a few other places but still reachable under certain
circumstances.

Change-Id: I1c8c6cccfd023bc1d839dc5d9544204c88f89c7e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
63c0fd2d — Angel Pons 6 months ago
mb/prodrive/hermes: Rename "internal audio" setting

The "internal audio connection" setting is actually about the front
panel audio. Rename functions and variables to reflect this.

Change-Id: I1be8f68ac3e8b91bc4983dc06daa37afb7bdf926
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin van Son <justin.van.son@prodrive-technologies.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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