~omasanori/coreboot

ccbe5307d80c28953132a02dae97f0a984ffecbc — Sumeet R Pawnikar 1 year, 4 months ago e5655a1
soc/intel/jasperlake: Enable processor thermal control using PCI_DEVFN

Enable processor thermal control using PCI dev path function instead of
Device4Enable parameter in devicetree. This change removes the dependency
on Device4Enable in devicetree. We can enable and disable this thermal
control using on and off support with PCI device entry in devicetree.

BRANCH=None
BUG=None
TEST=Built and tested on dedede board

Change-Id: I0463236996ad001af506c9966840b27fe44d60d2
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb => src/mainboard/google/dedede/variants/baseboard/devicetree.cb +0 -3
@@ 155,9 155,6 @@ chip soc/intel/jasperlake
		.tdp_pl2_override = 20,
	}"

	# Enable processor thermal control
	register "Device4Enable" = "1"

	register "tcc_offset" = "10"     # TCC of 90C

	# chipset_lockdown configuration

M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb => src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +0 -3
@@ 128,9 128,6 @@ chip soc/intel/jasperlake
	# Enable DPTF
	register "dptf_enable" = "1"

	# Enable Processor Thermal Control
	register "Device4Enable" = "1"

	# Add PL1 and PL2 values
	register "power_limits_config" = "{
		.tdp_pl1_override = 6,

M src/soc/intel/jasperlake/chip.h => src/soc/intel/jasperlake/chip.h +0 -1
@@ 142,7 142,6 @@ struct soc_intel_jasperlake_config {
	uint8_t SkipExtGfxScan;

	uint32_t GraphicsConfigPtr;
	uint8_t Device4Enable;

	/* HeciEnabled decides the state of Heci1 at end of boot
	 * Setting to 0 (default) disables Heci1 and hides the device from OS */

M src/soc/intel/jasperlake/fsp_params.c => src/soc/intel/jasperlake/fsp_params.c +3 -1
@@ 183,7 183,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
	if (params->ScsSdCardEnabled)
		params->SdCardPowerEnableActiveHigh = config->SdCardPowerEnableActiveHigh;

	params->Device4Enable = config->Device4Enable;
	/* Enable Processor Thermal Control */
	dev = pcidev_path_on_root(SA_DEVFN_DPTF);
	params->Device4Enable = is_dev_enabled(dev);

	/* Set TccActivationOffset */
	params->TccActivationOffset = config->tcc_offset;