~omasanori/coreboot

6fe3c06614dd423ad9a364c5f578e8c1764de65e — Angel Pons 1 year, 3 months ago 8cc39a5
nb/intel/haswell/finalize.c: Align MC locking with Broadwell

Broadwell uses a 32-bit or, so also use it on Haswell for consistency.
This has no effect because MRC already locks the memory controller down.

Tested on Asrock B85M Pro4, still boots and register is still locked.

Change-Id: Ida69cd9a95a658c24b4d2558dde88b94c167a3f9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46681
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1 files changed, 3 insertions(+), 3 deletions(-)

M src/northbridge/intel/haswell/finalize.c
M src/northbridge/intel/haswell/finalize.c => src/northbridge/intel/haswell/finalize.c +3 -3
@@ 17,6 17,9 @@ void intel_northbridge_haswell_finalize_smm(void)
	pci_or_config32(HOST_BRIDGE, TSEG,        1 << 0);
	pci_or_config32(HOST_BRIDGE, TOLUD,       1 << 0);

	/* Memory Controller Lockdown */
	MCHBAR32(MC_LOCK) |= 0x8f;

	MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0);	/* PAVP */
	MCHBAR32_OR(PCU_DDR_PTM_CTL, 1 << 5);	/* DDR PTM */
	MCHBAR32_OR(UMAGFXCTL, 1 << 0);		/* UMA GFX */


@@ 26,9 29,6 @@ void intel_northbridge_haswell_finalize_smm(void)
	MCHBAR32_OR(CRDTLCK, 1 << 0);
	MCHBAR32_OR(MCARBLCK, 1 << 0);

	/* Memory Controller Lockdown */
	MCHBAR8(MC_LOCK) = 0x8f;

	/* Read+write the following */
	MCHBAR32(VDMBDFBARKVM)  = MCHBAR32(VDMBDFBARKVM);
	MCHBAR32(VDMBDFBARPAVP) = MCHBAR32(VDMBDFBARPAVP);