#gen_fpga — a project boilerplate generator for the alchitry cu dev board

generates a template verilog project for the alchitry cu board. includes constraints for the built-in leds and inputs, and constraints for the alchitry io board. want just the constraints for the io board?

creates a project of the structure:

[PROJECT NAME]
├── constraints
│   ├── base.pcf
│   └── io.pcf
├── src
│   ├── top.v
│   ├── pulldown.v
│   ├── reset_conditioner.v
│   └── util.v
├── LICENSE
├── Makefile
├── README.md
└── .gitignore

#requirements

it uses the icestorm toolchain (yosys, nextpnr-ice40, icepack) and the command line version of alchitry loader extracted from alchitry-loader-gui.

to extract loader from alchitry-loader-gui:

1. download and extract the compiled tarball.
2. cd alchitry-loader-1.0.0/tools and copy out loader to somewhere in your PATH
3. cd ../driver
4. sudo cp 99-alchitry.rules /etc/udev/rules.d/

#installation

copy gen_fpga to a directory in your PATH.

#usage

gen_fpga [PROJECT_NAME]
cd [PROJECT_NAME]
make
make load # flashes the bitstream to the fpga

builds will be conducted in a directory called build in the project root. build artifacts are left, including the json from yosys, the icestorm asc bitstream format, the aggregated constraints file, and the final bitstream.

use make clean to cleanup build artifacts.

use make show to display a block diagram in your png viewer of choice.

#contributing

send patches and reports to ~nytpu/public-inbox@lists.sr.ht