generates a template verilog project for the alchitry cu board. includes constraints for the built-in leds and inputs, and constraints for the alchitry io board. want just the constraints for the io board?
creates a project of the structure:
[PROJECT NAME] ├── constraints │ ├── base.pcf │ └── io.pcf ├── src │ ├── top.v │ ├── pulldown.v │ ├── reset_conditioner.v │ └── util.v ├── LICENSE ├── Makefile ├── README.md └── .gitignore
loader from alchitry-loader-gui:
cd alchitry-loader-1.0.0/toolsand copy out
loaderto somewhere in your
sudo cp 99-alchitry.rules /etc/udev/rules.d/
copy gen_fpga to a directory in your PATH.
gen_fpga [PROJECT_NAME] cd [PROJECT_NAME] make make load # flashes the bitstream to the fpga
builds will be conducted in a directory called
build in the project root.
build artifacts are left, including the json from yosys, the icestorm asc
bitstream format, the aggregated constraints file, and the final bitstream.
make clean to cleanup build artifacts.
make show to display a block diagram in your png viewer of choice.
send patches and reports to ~firstname.lastname@example.org