~maelkum/riscv-box

Simple RISC-V emulator for educational purposes
Test SB, SH, SW instructions
Add a printf syscall
Remove redundant if

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#RISC-V box

A simple RISC-V emulator for educational purposes.


See the code in src/main.cpp for an example of machine code generation. There is currently no assembler available so you have to its job manually.


#Instruction support

Only 32-bit instructions are supported. RV64I and RVC are not implemented.

#RV32I

Shifts:

  • sll
  • slli
  • srl
  • srli
  • sra
  • srai

Arithmetic:

  • add ✓
  • addi ✓
  • sub
  • lui ✓
  • auipc ✓

Logical:

  • xor
  • xori
  • or
  • ori
  • and ✓
  • andi ✓

Compare:

  • slt
  • slti
  • sltu
  • sltiu

Branches:

  • beq ✓
  • bne ✓
  • blt ✓
  • bge ✓
  • bltu ✓
  • bgeu ✓

Jump & link:

  • jal ✓
  • jalr ✓

Synchronisation:

  • fence
  • fence.i

Environment:

  • ecall ✓
  • ebreak ✓

Loads:

  • lb ✓
  • lh ✓
  • lbu ✓
  • lhu ✓
  • lw ✓

Stores:

  • sb
  • sh
  • sw

Control Status Register:

  • csrrw
  • csrrs
  • csrrc
  • csrrwi
  • csrrsi
  • crrsci

#Literature

The RISC-V Reader. An Open Architecture Atlas by David Patterson, Andrew Waterman


This is Free Software published under either version 3 of the GNU General Public License, or (at your option) any later version.

Copyright (C) 2021 Marek Marecki