A simple RISC-V emulator for educational purposes.
See the code in
src/main.cpp for an example of machine code generation. There
is currently no assembler available so you have to its job manually.
Only 32-bit instructions are supported. RV64I and RVC are not implemented.
Jump & link:
Control Status Register:
The RISC-V Reader. An Open Architecture Atlas by David Patterson, Andrew Waterman
This is Free Software published under either version 3 of the GNU General Public License, or (at your option) any later version.
Copyright (C) 2021 Marek Marecki