~laumann/hadb

6beb0568ef285823ff4613c6f3abefa181fd7d68 — Thomas Bracht Laumann Jespersen 1 year, 2 months ago 32472ba
format/dwarf: cleanup + rename "statemachine" -> "registers"
2 files changed, 44 insertions(+), 48 deletions(-)

M format/dwarf/decode.ha
M format/dwarf/types.ha
M format/dwarf/decode.ha => format/dwarf/decode.ha +40 -44
@@ 27,24 27,24 @@ export fn newdecoder(
		line_range = line_range,
		default_is_stmt = default_is_stmt,
		standard_opcode_lengths = standard_opcode_lengths,
		state = statemachine { ... }
		regs = registers { ... }
	};
	reset(&dec);
	return dec;
};

// Reset the state machine in the decoder
// Reset the registers in the decoder
export fn reset(dec: *decoder) void = {
	dec.state.addr = 0;
	dec.state.file = 1;
	dec.state.line = 1;
	dec.state.column = 0;
	dec.state.is_stmt = dec.default_is_stmt;
	dec.state.end_sequence = false;
	dec.regs.addr = 0;
	dec.regs.file = 1;
	dec.regs.line = 1;
	dec.regs.column = 0;
	dec.regs.is_stmt = dec.default_is_stmt;
	dec.regs.end_sequence = false;
};

export fn new(is_stmt: bool) statemachine = {
	return statemachine {
export fn new(is_stmt: bool) registers = {
	return registers {
		addr = 0,
		file = 1,
		line = 1,


@@ 280,14 280,14 @@ export fn free_lineprogramheader(lph: *lineprogramheader) void = {
	free(lph.file_names);
};

fn newline(state: *statemachine) line = line {
	addr = state.addr,
	file = state.file,
	line = state.line,
	column = state.column,
	is_stmt = state.is_stmt,
	basic_block = state.basic_block,
	end_sequence = state.end_sequence,
fn newline(regs: *registers) line = line {
	addr = regs.addr,
	file = regs.file,
	line = regs.line,
	column = regs.column,
	is_stmt = regs.is_stmt,
	basic_block = regs.basic_block,
	end_sequence = regs.end_sequence,
};

export fn decode_op(dec: *decoder) (op | io::EOF | error) = {


@@ 358,17 358,16 @@ export fn decode_op(dec: *decoder) (op | io::EOF | error) = {
			// corresponding to special opcode 255 by the
			// minimum_instruction_length field of the
			// header, and adds the result to the address
			// register of the state machine.
			// register

			let (_, ainc) = decode_special(255, dec.opcode_base,
				dec.line_base, dec.line_range);
			return ainc : constaddpc : op;

		case lns::FIXED_ADVANCE_PC =>
			// takes a single uhalf (unencoded) operand and
			// adds it to the address register of the state
			// machine. Does *not* multiply the operand by
			// min_instr_length
			// takes a single uhalf (unencoded) operand and adds it
			// to the address register. Does *not* multiply the
			// operand by min_instr_length
			let buf = [0u8, 0];
			readexact(dec.src, &buf)?;
			let ainc = endian::host.getu16(&buf);


@@ 379,7 378,6 @@ export fn decode_op(dec: *decoder) (op | io::EOF | error) = {
			// Unhandled opcode - we should consume as many
			// uleb128 operands as given in
			// standard_opcode_lengths
			//fmt::printfln("unknown/unhandled opcode {}", op)!;
			let n = dec.standard_opcode_lengths[bop];
			for (let i = 0z; i < n; i += 1)
				decodeuleb128(dec)?;


@@ 394,46 392,44 @@ export fn decode_op(dec: *decoder) (op | io::EOF | error) = {
export fn decode_lines(dec: *decoder) ([]line | error) = {
	let lines: []line = [];
	let err = true;
	defer if (err) {
		free(lines);
	};
	defer if (err) free(lines);

	for (true) match (decode_op(dec)?) {
	case let op: op =>
		match (op) {
		case let sp : special =>
			let (addr_inc, line_inc) = sp;
			dec.state.addr += dec.minimum_instruction_length * addr_inc : size;
			dec.state.line = (dec.state.line : i64 + line_inc : i64) : size;
			append(lines, newline(&dec.state));
			dec.state.basic_block = false;
			dec.regs.addr += dec.minimum_instruction_length * addr_inc : size;
			dec.regs.line = (dec.regs.line : i64 + line_inc : i64) : size;
			append(lines, newline(&dec.regs));
			dec.regs.basic_block = false;
		case endsequence =>
			dec.state.end_sequence = true;
			append(lines, newline(&dec.state));
			dec.regs.end_sequence = true;
			append(lines, newline(&dec.regs));
			reset(dec);
		case extunknown =>
			void; // FIXME what to do here?
		case let addr : setaddr =>
			dec.state.addr = addr;
			dec.regs.addr = addr;
		case copy =>
			append(lines, newline(&dec.state));
			dec.state.basic_block = false;
			append(lines, newline(&dec.regs));
			dec.regs.basic_block = false;
		case let addr_inc : advancepc =>
			dec.state.addr += (addr_inc * dec.minimum_instruction_length) : size;
			dec.regs.addr += (addr_inc * dec.minimum_instruction_length) : size;
		case let line_inc : advanceline =>
			dec.state.line = (dec.state.line : i64 + line_inc : i64) : size;
			dec.regs.line = (dec.regs.line : i64 + line_inc : i64) : size;
		case let file : setfile =>
			dec.state.file = file;
			dec.regs.file = file;
		case let col : setcol =>
			dec.state.column = col;
			dec.regs.column = col;
		case negstmt =>
			dec.state.is_stmt = !dec.state.is_stmt;
			dec.regs.is_stmt = !dec.regs.is_stmt;
		case setbasicblock =>
			dec.state.basic_block = true;
			dec.regs.basic_block = true;
		case let addr_inc : constaddpc =>
			dec.state.addr += dec.minimum_instruction_length * addr_inc : size;
			dec.regs.addr += dec.minimum_instruction_length * addr_inc : size;
		case let addr_inc : fixadvancepc =>
			dec.state.addr += addr_inc;
			dec.regs.addr += addr_inc;
		case stdunknown =>
			void; // FIXME what to do here?
		case => abort();

M format/dwarf/types.ha => format/dwarf/types.ha +4 -4
@@ 8,11 8,11 @@ export type unexpectedeof = !void;
// Tagged union of all possible errors
export type error = !(unexpectedeof | io::error);

// state machine for the Statement Program.
// registers for the Statement Program.
// 
// The goal of the Statement Program is to build a matrix representing one
// compilation unit.
export type statemachine = struct {
export type registers = struct {
	addr: size, // program counter
	file: size, // spec: unsigned int, gives identity of the source file corresponding to machine instruction.
	line: size, // spec: source line number, starts at 1


@@ 106,8 106,8 @@ export type decoder = struct {

	standard_opcode_lengths: []u8,

	// The state machine
	state: statemachine,
	// The registers
	regs: registers,
};

// DWARF 2.0.0 Figure 34