Note: application code lives here: SoftConsole/SB0_MSS_CM3/SB0_MSS_CM3_app/

• SPP StimuliBox

  • Functional Requirements

    • Drive a set of relays given commands over the network.
    • update firmware (over JTAG)
    • serial console for configuring the IP address and other settings
    • use non-volatile ram for storing settings
    • talk TCP/IP (DHCP and static ip)
    • simple commands for setting and querying the current status
      • set will be a vector of bytes representing the states to set each relay to.
        • The firmware will verify the incoming state.
        • Q: how will we verify the incoming state vector?
      • get will also be a vector of bytes representing the current state of the stimuli box. plus maybe some addtional information.
      • Q: what might this additional information consist of?
    • We will also be talking to external relay boxes.
      • These boxes will probably take commands via a gated shift register.
        • Q: does that mean we'll need a UART for each box?
        • Q: how will we break them out?
      • They will also provide state information
        • Q: how will we read the information from the relay boxes?

  • Implementation Notes

    • write custom linker script
    • write very basic rtos to support lwip
    • use lwip
    • write a bootloader that will load an image from the serial port to the DDR memory and then jump to it. This could be used for rapid prototyping if we exceed the RAM size.
    • don't use libc if at all possible; especially don't use the i/o routines

  • Milestones (SB0, SB1, etc...)

    • SB0

      • configure hardware
        • ethernet
        • ddr
        • hard gpio led blink
        • hard uart
      • software
        • blink hard gpio leds (using systick)
        • verify ddr r/w
        • verify ethernet link
        • verify uart operation

    • SB1

      • hardware
        • no change
      • software, same as SB0, plus:
        • read and write settings into eNVM
        • integrate lwip into project without using a RTOS

    • SB2

      • hardware
        • no change
      • software, same as SB1, plus:
        • create serial console
        • create simple command protocol for setting the LED over the network

    • SB3

      • hardware, same as SB2
      • software, same as SB2, plus
        • store system settings on flash

    • SB4

      • hardware, same as SB3, plus
        • solder unshrouded header to breakout area (24 position, 2mm pitch)
        • create a breadboard with the 74HC08, 74HC154, 74HC126 & 74HC573 chips and some solid state relays.
          • Materials we'll need:
            • Muriatic acid
            • Hydrogen Peroxide 2%
            • GBC BadgeMates laminator
            • plastic vise
            • Hammermill Color Laser Gloss Paper
            • Baking Soda
            • pyrex dish
            • plastic measuring cups
            • steel wool #0000
            • 3m heavy duty stripping pads
            • clear enamel spray paint
        • connect the two via a 2x24 cable
      • software, same as SB3, plus
        • write driver for external logic hardware. maybe this could be a APB peripheral in the fabric?
        • On-board flash-based boot-loader
          • smart enough to write and read files to the onboard NVM or DDR
        • move code into Makefile and Emacs
        • find a Mac OS X Cortex M3 toolchain

  • BUGS

    • it seems silly that the system hangs when the cable is unplugged.

    • I think there is a case where the system gets stuck in the ethernet ISR. Maybe bumping the priority of the ethernet ISR down a below SysTick would help it get "unstuck".

      I saw it busy waiting for a buffer to become free.

    • Unplugging and replugging the network cable doesn't seem to cause a link-down notification. Thus, we can't ask for our DHCP address again. Normally, this isn'y a problem, but on the Physics network, it is.

      To fix this we must add a task that polls the PHY to determine the link status and then calls netif_set_link_[up|down] in the lwip stack. This should fix the problem.

    • write memory locations

    • dump statistics and errors.

• Cortex-M3 Notes

  • How to setup SysTick

    • Since SysTick_Handler is weak-linked, we just need to define a function with the following signature, void SysTick_Handler(void);
    • SysTick can source two different clocks
      • FPLL: This is the output of MSS_CCC and can be selected by setting bit 25 of SYSREG->M3_CR and setting bit 2 of SysTick->CTRL.
      • STCLK: This is a clock signal that is divided down based on bits 26 and 27 of SYSREG->M3_CR. It's enabled clearing bit 25 of the aforementioned register and clearing bit 2 of SysTick->CTRL.
      • When talking about external reference and processor clocks; external refers to STCLK and processor refers to MSS_CCC.
    • SysTick->LOAD is a 24bit quantity that is (re)loaded when the counter reaches 0
    • Suggested order
      • Configure SYSREG->M3_CR
      • Set SysTick->LOAD
      • Set SysTick->VAL to 0
      • Set SysTick->CTRL bits 0 & 1 and possibly 2 if you want to use the FPLL instead of the external clock
    • If bit 25 of SYSREG->M3_CR is set, then SysTick will always use FPLL regardless of bit 2 in SysTick->CTRL.

  • #How to port lwIP to a bare metal SmartFusion2 Cortex-M3

• General Notes and Questions [100%]

  • [X] determine if the MSS configures the DDR or if the soft IP does. it looks like the smartfusion2 uses the soft IP to connect the MDDR configuration registers to the MSS who does the actual configuration.

  • [X] I/O banks and voltages?
    Each I/O bank has it's own VCC and drive capabilities

  • [X] constraint file directives? Where to find them? there also is a graphical constraint editor in SOC

  • [X] how do clocks relate to the constraint file?
    you can define clocks and skew and such in the clock constraint file

  • [X] how to connect the MAC to the off-chip PHY? connect the managment interface through a BIBUF (multiplexes MDIO) connect the MAC pins to the PHY pins via the constraints file make sure the logic voltage is 2.5V or you won't be able to connect them promote the mangement pins to the top-level

  • [X] what is SERDES? what is a "lane"? SERDES is used to drive PCIe and other fast busses