~joshrig/seven-segment

0183e4209ca0d2bbdfdec7a9628aea9f3ae8314a — Joshua Lynch 3 months ago b4d1c16 master
code cleanup
2 files changed, 25 insertions(+), 26 deletions(-)

M seven-segment.srcs/sources_1/new/sseg_top.vhd
M seven-segment.xpr
M seven-segment.srcs/sources_1/new/sseg_top.vhd => seven-segment.srcs/sources_1/new/sseg_top.vhd +19 -24
@@ 2,51 2,46 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;



entity sseg_top is
  port(
    CLK        : in std_logic;
    CPU_RESETN : in std_logic;
    SW         : in std_logic;
    CLK        : in  std_logic;
    CPU_RESETN : in  std_logic;
    SW         : in  std_logic;
    SS         : out std_logic_vector(6 downto 0);
    DP         : out std_logic;
    AN         : out std_logic_vector(7 downto 0)
  );
end sseg_top;



architecture Behavioral of sseg_top is
  signal cnt : unsigned(31 downto 0);
  signal cnt : unsigned        (15 downto 0);
  signal ano : std_logic_vector(7 downto 0);
begin

  process (CLK, CPU_RESETN, SW, cnt, ano)
  begin
    if CPU_RESETN = '0' then
      cnt <= x"00000000";
      ano <= "01111111";
      SS <= "1111111";
      cnt <= (others => '0');
      ano <= (others => '1');
      SS  <= (others => '1');
    else
      if CLK'event and CLK = '1' then
        if cnt = x"0000ffff" then
        if ano = x"ff" then
          ano <= "01111111";
        end if;
        
        if cnt = x"ffff" then
          ano <= ano(0) & ano(7 downto 1);
          cnt <= x"00000000";
        else
          cnt <= cnt + 1;
          cnt <= (others => '0');
        end if;

        cnt <= cnt + 1;
      end if;

      -- if ano = "01111111" then
      --   let <= "1000110";
      -- elsif ano = "10111111" then
      --   let <= "0001000";
      -- elsif ano = "11011111" or ano = "11101111" then
      --   let <= "0101111";
      -- elsif ano = "11110111" then
      --   let <= "1001111";
      -- elsif ano = "11111011" then
      --   let <= "0000110";
      -- else
      --   let <= "1111111";
      -- end if;
      if SW = '0' then
        case ano is
          when "01111111" =>

M seven-segment.xpr => seven-segment.xpr +6 -2
@@ 179,7 179,9 @@
  <Runs Version="1" Minor="21">
    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
      <Strategy Version="1" Minor="2">
        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
          <Desc>Vivado Synthesis Defaults</Desc>
        </StratHandle>
        <Step Id="synth_design"/>
      </Strategy>
      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>


@@ 189,7 191,9 @@
    </Run>
    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 32 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
      <Strategy Version="1" Minor="2">
        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
          <Desc>Default settings for Implementation.</Desc>
        </StratHandle>
        <Step Id="init_design"/>
        <Step Id="opt_design"/>
        <Step Id="power_opt_design"/>