~jleightcap/eateremu-verilog

modules with testbench
basic module structure
hdl-checker linting pass
final, FINAL, typo fixing!!!
okay, /now/ don't have to escape those underscores
in verbatim blocks of md don't need \_, whoops
hopefully final formatting fix
add GPLv2, formatting in README
update README with example usage
add README, clear RAM testing memory
working conditional jumps
seems like all instructions work!
next step is to write an assembler for more thorough testing.
unconditional jump works
all that's left is conditional jumps and flags register
move high Z to logic 0 conversion to register
rather than updating values stored in A, B in the ALU, just store the right values
woo ALU works!
turns out that leaving the output port of B floating was bad...
just not connecting != defaults to 0
a high Z on the output control line just makes a mess, hardcode to 1'b0
All operations but ALU work
Think because it's asynchronous, might just model on clock edges for now
playing around with high impedence conversions, otherwise Verilog +/- operations fail
working LDI, OUT, HLT
debugging RAM and ALU operations
only connect lower nibble of IR to bus
LDI now works
second instruction seems to freeze...?
fix clocking of control logic bug
remember in the build where the control clock is offset 180 degrees from the system clock?
because I didn't!
Now registers actually latch at the appropriate control signal.
Overhaul, working fetch stage
Actually learn Verilog lol whoops
add resets to registers and PC
instead of initializing as a sepearte case, just toggle clear at #0
fix initial control word bug
initialize control word to 16'b0, otherwise the undefined signals skip the first CO | MI
next bug is that the program counter doesn't output to the bus
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