From e2fd21bbf665cc26b0fabf544bec91caab723b5b Mon Sep 17 00:00:00 2001 From: jleightcap Date: Sun, 14 Nov 2021 03:03:46 -0500 Subject: [PATCH] basic module structure --- .gitignore | 5 + Makefile | 15 +- alu.v | 18 --- clkdiv.v | 11 ++ control.v | 98 ----------- cpu.v | 8 + eateremu.blif | 336 ++++++++++++++++++++++++++++++++++++++ eateremu.v | 150 ++++------------- eateremu_tb | 411 +++++++++++++++++++++++++++++++++++++++++++++++ eateremu_tb.v | 54 ++----- icebreaker.pcf | 109 +++++++++++++ main.mk | 51 ++++++ mem_register.v | 20 --- programcounter.v | 25 --- ram.v | 37 ----- register8.v | 29 ---- seven_seg_hex.v | 28 ++++ seven_seg_mux.v | 24 +++ 18 files changed, 1031 insertions(+), 398 deletions(-) create mode 100644 .gitignore delete mode 100644 alu.v create mode 100644 clkdiv.v delete mode 100644 control.v create mode 100644 cpu.v create mode 100644 eateremu.blif create mode 100755 eateremu_tb create mode 100644 icebreaker.pcf create mode 100644 main.mk delete mode 100644 mem_register.v delete mode 100644 programcounter.v delete mode 100644 ram.v delete mode 100644 register8.v create mode 100644 seven_seg_hex.v create mode 100644 seven_seg_mux.v diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..817de2a --- /dev/null +++ b/.gitignore @@ -0,0 +1,5 @@ +*.asc +*.bin +*.json +*.log +*.rpt diff --git a/Makefile b/Makefile index 227c357..0034d60 100644 --- a/Makefile +++ b/Makefile @@ -1,13 +1,6 @@ -BIN := eateremu_tb +PROJ = eateremu -$(BIN): - iverilog -o $(BIN) $(BIN).v +PIN_DEF = icebreaker.pcf +DEVICE = up5k -verbose: - iverilog -o $(BIN) -DVERBOSE $(BIN).v - -test: $(BIN) - vvp $(BIN) - -clean: - rm -f $(BIN) $(BIN).vcd +include main.mk diff --git a/alu.v b/alu.v deleted file mode 100644 index 99488d2..0000000 --- a/alu.v +++ /dev/null @@ -1,18 +0,0 @@ -module Alu ( - input clk, - input[7:0] a, - input[7:0] b, - input su, - input out, - output[7:0] alu_out, - output ovf, - output zf -); - wire[8:0] result; - - assign result = su ? (a - b) : (a + b); - - assign alu_out = out ? result : 8'hzz; - assign ovf = result[8]; - assign zf = result == 0; -endmodule diff --git a/clkdiv.v b/clkdiv.v new file mode 100644 index 0000000..a7bbf63 --- /dev/null +++ b/clkdiv.v @@ -0,0 +1,11 @@ +module clkdiv( + input clk, + output clkout + ); + +reg [15:0] counter; +assign clkout = counter[15]; + +always @(posedge clk) + counter <= counter+1; +endmodule diff --git a/control.v b/control.v deleted file mode 100644 index 562f02a..0000000 --- a/control.v +++ /dev/null @@ -1,98 +0,0 @@ -module control ( - input clk, - input ovf, - input zf, - input[3:0] instruction, - output reg[15:0] ctrl_data -); - parameter HLT = 16'b1000000000000000; // Halt clock - parameter MI = 16'b0100000000000000; // Memory address register in - parameter RI = 16'b0010000000000000; // RAM data in - parameter RO = 16'b0001000000000000; // RAM data out - parameter IO = 16'b0000100000000000; // Instruction register out - parameter II = 16'b0000010000000000; // Instruction register in - parameter AI = 16'b0000001000000000; // A register in - parameter AO = 16'b0000000100000000; // A register out - parameter EO = 16'b0000000010000000; // ALU out - parameter SU = 16'b0000000001000000; // ALU subtract - parameter BI = 16'b0000000000100000; // B register in - parameter OI = 16'b0000000000010000; // Output register in - parameter CE = 16'b0000000000001000; // Program counter enable - parameter CO = 16'b0000000000000100; // Program counter out - parameter J = 16'b0000000000000010; // Jump (program counter in) - parameter FI = 16'b0000000000000001; // Flags in - - reg[2:0] count; - - initial count = 3'b000; - initial ctrl_data = 16'b0000000000000000; - - `ifdef VERBOSE integer instruction_num = 0; `endif - - always @(posedge clk) begin - case (count) - 3'b000: begin - `ifdef VERBOSE $display(instruction_num); instruction_num++; `endif - ctrl_data <= MI | CO; - end - 3'b001: begin - ctrl_data <= RO | II | CE; - end - 3'b010: begin - begin case (instruction) - 4'b0000: /* NOP 2 */ ctrl_data <= 0; - 4'b0001: /* LDA 2 */ ctrl_data <= IO | MI; - 4'b0010: /* ADD 2 */ ctrl_data <= IO | MI; - 4'b0011: /* SUB 2 */ ctrl_data <= IO | MI; - 4'b0100: /* STA 2 */ ctrl_data <= IO | MI; - 4'b0101: /* LDI 2 */ ctrl_data <= IO | AI; - 4'b0110: /* JMP 2 */ ctrl_data <= IO | J; - 4'b0111: /* JC 2 */ - begin - if (ovf) ctrl_data <= IO | J; - else ctrl_data <= 0; - end - 4'b1000: /* JZ 2 */ - begin - if (zf) ctrl_data <= IO | J; - else ctrl_data <= 0; - end - 4'b1110: /* OUT 2 */ ctrl_data <= AO | OI; - 4'b1111: /* HLT 2 */ ctrl_data <= HLT; - default: ctrl_data <= 0; - endcase end - end - 3'b011: begin case (instruction) - 4'b0000: /* NOP 3 */ ctrl_data <= 0; - 4'b0001: /* LDA 3 */ ctrl_data <= RO | AI; - 4'b0010: /* ADD 3 */ ctrl_data <= RO | BI; - 4'b0011: /* SUB 3 */ ctrl_data <= RO | BI; - 4'b0100: /* STA 3 */ ctrl_data <= AO | RI; - 4'b0101: /* LDI 3 */ ctrl_data <= 0; - 4'b0110: /* JMP 3 */ ctrl_data <= 0; - 4'b0111: /* JC 3 */ ctrl_data <= 0; - 4'b1000: /* JZ 3 */ ctrl_data <= 0; - 4'b1110: /* OUT 3 */ ctrl_data <= 0; - 4'b1111: /* HLT 3 */ ctrl_data <= 0; - default: ctrl_data <= 0; - endcase end - 3'b100: begin case (instruction) - 4'b0000: /* NOP 4 */ ctrl_data <= 0; - 4'b0001: /* LDA 4 */ ctrl_data <= 0; - 4'b0010: /* ADD 4 */ ctrl_data <= EO | AI | FI; - 4'b0011: /* SUB 4 */ ctrl_data <= EO | AI | SU | FI; - 4'b0100: /* STA 4 */ ctrl_data <= 0; - 4'b0101: /* LDI 4 */ ctrl_data <= 0; - 4'b0110: /* JMP 4 */ ctrl_data <= 0; - 4'b0111: /* JC 4 */ ctrl_data <= 0; - 4'b1000: /* JZ 4 */ ctrl_data <= 0; - 4'b1110: /* OUT 4 */ ctrl_data <= 0; - 4'b1111: /* HLT 4 */ ctrl_data <= 0; - default: ctrl_data <= 0; - endcase end - default: - ctrl_data <= 0; - endcase - count <= count + 1; - end -endmodule diff --git a/cpu.v b/cpu.v new file mode 100644 index 0000000..acb7728 --- /dev/null +++ b/cpu.v @@ -0,0 +1,8 @@ +module cpu( + input cpu_clk, + output [7:0] bus +); + +assign bus = 8'h42; + +endmodule diff --git a/eateremu.blif b/eateremu.blif new file mode 100644 index 0000000..9ac1926 --- /dev/null +++ b/eateremu.blif @@ -0,0 +1,336 @@ +# Generated by Yosys 0.9+4247 (git sha1 f76aad9, clang 11.0.1-2 -fPIC -Os) + +.model top +.inputs CLK +.outputs seg[0] seg[1] seg[2] seg[3] seg[4] seg[5] seg[6] ca +.names $false +.names $true +1 +.names $undef +.gate SB_DFF C=display.clk D=ca_SB_DFF_Q_D Q=ca +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:36.15-42.2|seven_seg_mux.v:12.1-22.9|/home/jleightcap/sft/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=ca O=ca_SB_DFF_Q_D +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/home/jleightcap/sft/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_DFF C=CLK D=display.clk_SB_LUT4_I2_O[15] Q=display.clk +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:31.8-34.2|clkdiv.v:9.1-10.23|/home/jleightcap/sft/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_LUT4 I0=$false I1=$false I2=display.clk I3=display.clk_SB_LUT4_I2_I3[15] O=display.clk_SB_LUT4_I2_O[15] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:31.8-34.2|clkdiv.v:10.13-10.22|/home/jleightcap/sft/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/home/jleightcap/sft/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=$false I3=display_clockGen.counter[0] O=display.clk_SB_LUT4_I2_O[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/home/jleightcap/sft/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" +.param LUT_INIT 0000000011111111 +.gate SB_LUT4 I0=$false I1=$false I2=display_clockGen.counter[11] I3=display.clk_SB_LUT4_I2_I3[11] O=display.clk_SB_LUT4_I2_O[11] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:31.8-34.2|clkdiv.v:10.13-10.22|/home/jleightcap/sft/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/home/jleightcap/sft/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=display_clockGen.counter[2] I3=display.clk_SB_LUT4_I2_I3[2] O=display.clk_SB_LUT4_I2_O[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:31.8-34.2|clkdiv.v:10.13-10.22|/home/jleightcap/sft/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/home/jleightcap/sft/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=display_clockGen.counter[1] I3=display_clockGen.counter[0] O=display.clk_SB_LUT4_I2_O[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:31.8-34.2|clkdiv.v:10.13-10.22|/home/jleightcap/sft/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/home/jleightcap/sft/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=display_clockGen.counter[14] I3=display.clk_SB_LUT4_I2_I3[14] O=display.clk_SB_LUT4_I2_O[14] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:31.8-34.2|clkdiv.v:10.13-10.22|/home/jleightcap/sft/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/home/jleightcap/sft/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=display_clockGen.counter[13] I3=display.clk_SB_LUT4_I2_I3[13] O=display.clk_SB_LUT4_I2_O[13] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:31.8-34.2|clkdiv.v:10.13-10.22|/home/jleightcap/sft/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/home/jleightcap/sft/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=display_clockGen.counter[12] I3=display.clk_SB_LUT4_I2_I3[12] O=display.clk_SB_LUT4_I2_O[12] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:31.8-34.2|clkdiv.v:10.13-10.22|/home/jleightcap/sft/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/home/jleightcap/sft/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=display_clockGen.counter[10] I3=display.clk_SB_LUT4_I2_I3[10] O=display.clk_SB_LUT4_I2_O[10] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:31.8-34.2|clkdiv.v:10.13-10.22|/home/jleightcap/sft/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/home/jleightcap/sft/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=display_clockGen.counter[9] I3=display.clk_SB_LUT4_I2_I3[9] O=display.clk_SB_LUT4_I2_O[9] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:31.8-34.2|clkdiv.v:10.13-10.22|/home/jleightcap/sft/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/home/jleightcap/sft/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=display_clockGen.counter[8] I3=display.clk_SB_LUT4_I2_I3[8] O=display.clk_SB_LUT4_I2_O[8] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:31.8-34.2|clkdiv.v:10.13-10.22|/home/jleightcap/sft/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/home/jleightcap/sft/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=display_clockGen.counter[7] I3=display.clk_SB_LUT4_I2_I3[7] O=display.clk_SB_LUT4_I2_O[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:31.8-34.2|clkdiv.v:10.13-10.22|/home/jleightcap/sft/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/home/jleightcap/sft/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=display_clockGen.counter[6] I3=display.clk_SB_LUT4_I2_I3[6] O=display.clk_SB_LUT4_I2_O[6] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:31.8-34.2|clkdiv.v:10.13-10.22|/home/jleightcap/sft/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/home/jleightcap/sft/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=display_clockGen.counter[5] I3=display.clk_SB_LUT4_I2_I3[5] O=display.clk_SB_LUT4_I2_O[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:31.8-34.2|clkdiv.v:10.13-10.22|/home/jleightcap/sft/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/home/jleightcap/sft/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=display_clockGen.counter[4] I3=display.clk_SB_LUT4_I2_I3[4] O=display.clk_SB_LUT4_I2_O[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:31.8-34.2|clkdiv.v:10.13-10.22|/home/jleightcap/sft/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/home/jleightcap/sft/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_LUT4 I0=$false I1=$false I2=display_clockGen.counter[3] I3=display.clk_SB_LUT4_I2_I3[3] O=display.clk_SB_LUT4_I2_O[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:31.8-34.2|clkdiv.v:10.13-10.22|/home/jleightcap/sft/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/home/jleightcap/sft/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" +.param LUT_INIT 0110100110010110 +.gate SB_DFF C=display.clk D=ca Q=display.segout[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:36.15-42.2|seven_seg_mux.v:12.1-22.9|/home/jleightcap/sft/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_CARRY CI=display_clockGen.counter[0] CO=display.clk_SB_LUT4_I2_I3[2] I0=$false I1=display_clockGen.counter[1] +.attr src "eateremu.v:31.8-34.2|clkdiv.v:10.13-10.22|/home/jleightcap/sft/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=display.clk_SB_LUT4_I2_I3[9] CO=display.clk_SB_LUT4_I2_I3[10] I0=$false I1=display_clockGen.counter[9] +.attr src "eateremu.v:31.8-34.2|clkdiv.v:10.13-10.22|/home/jleightcap/sft/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=display.clk_SB_LUT4_I2_I3[8] CO=display.clk_SB_LUT4_I2_I3[9] I0=$false I1=display_clockGen.counter[8] +.attr src "eateremu.v:31.8-34.2|clkdiv.v:10.13-10.22|/home/jleightcap/sft/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=display.clk_SB_LUT4_I2_I3[12] CO=display.clk_SB_LUT4_I2_I3[13] I0=$false I1=display_clockGen.counter[12] +.attr src "eateremu.v:31.8-34.2|clkdiv.v:10.13-10.22|/home/jleightcap/sft/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=display.clk_SB_LUT4_I2_I3[11] CO=display.clk_SB_LUT4_I2_I3[12] I0=$false I1=display_clockGen.counter[11] +.attr src "eateremu.v:31.8-34.2|clkdiv.v:10.13-10.22|/home/jleightcap/sft/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=display.clk_SB_LUT4_I2_I3[10] CO=display.clk_SB_LUT4_I2_I3[11] I0=$false I1=display_clockGen.counter[10] +.attr src "eateremu.v:31.8-34.2|clkdiv.v:10.13-10.22|/home/jleightcap/sft/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=display.clk_SB_LUT4_I2_I3[7] CO=display.clk_SB_LUT4_I2_I3[8] I0=$false I1=display_clockGen.counter[7] +.attr src "eateremu.v:31.8-34.2|clkdiv.v:10.13-10.22|/home/jleightcap/sft/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=display.clk_SB_LUT4_I2_I3[6] CO=display.clk_SB_LUT4_I2_I3[7] I0=$false I1=display_clockGen.counter[6] +.attr src "eateremu.v:31.8-34.2|clkdiv.v:10.13-10.22|/home/jleightcap/sft/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=display.clk_SB_LUT4_I2_I3[5] CO=display.clk_SB_LUT4_I2_I3[6] I0=$false I1=display_clockGen.counter[5] +.attr src "eateremu.v:31.8-34.2|clkdiv.v:10.13-10.22|/home/jleightcap/sft/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=display.clk_SB_LUT4_I2_I3[4] CO=display.clk_SB_LUT4_I2_I3[5] I0=$false I1=display_clockGen.counter[4] +.attr src "eateremu.v:31.8-34.2|clkdiv.v:10.13-10.22|/home/jleightcap/sft/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=display.clk_SB_LUT4_I2_I3[3] CO=display.clk_SB_LUT4_I2_I3[4] I0=$false I1=display_clockGen.counter[3] +.attr src "eateremu.v:31.8-34.2|clkdiv.v:10.13-10.22|/home/jleightcap/sft/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=display.clk_SB_LUT4_I2_I3[2] CO=display.clk_SB_LUT4_I2_I3[3] I0=$false I1=display_clockGen.counter[2] +.attr src "eateremu.v:31.8-34.2|clkdiv.v:10.13-10.22|/home/jleightcap/sft/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=display.clk_SB_LUT4_I2_I3[14] CO=display.clk_SB_LUT4_I2_I3[15] I0=$false I1=display_clockGen.counter[14] +.attr src "eateremu.v:31.8-34.2|clkdiv.v:10.13-10.22|/home/jleightcap/sft/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_CARRY CI=display.clk_SB_LUT4_I2_I3[13] CO=display.clk_SB_LUT4_I2_I3[14] I0=$false I1=display_clockGen.counter[13] +.attr src "eateremu.v:31.8-34.2|clkdiv.v:10.13-10.22|/home/jleightcap/sft/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" +.gate SB_DFF C=CLK D=display.clk_SB_LUT4_I2_O[14] Q=display_clockGen.counter[14] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:31.8-34.2|clkdiv.v:9.1-10.23|/home/jleightcap/sft/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=CLK D=display.clk_SB_LUT4_I2_O[13] Q=display_clockGen.counter[13] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:31.8-34.2|clkdiv.v:9.1-10.23|/home/jleightcap/sft/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=CLK D=display.clk_SB_LUT4_I2_O[4] Q=display_clockGen.counter[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:31.8-34.2|clkdiv.v:9.1-10.23|/home/jleightcap/sft/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=CLK D=display.clk_SB_LUT4_I2_O[3] Q=display_clockGen.counter[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:31.8-34.2|clkdiv.v:9.1-10.23|/home/jleightcap/sft/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=CLK D=display.clk_SB_LUT4_I2_O[2] Q=display_clockGen.counter[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:31.8-34.2|clkdiv.v:9.1-10.23|/home/jleightcap/sft/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=CLK D=display.clk_SB_LUT4_I2_O[1] Q=display_clockGen.counter[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:31.8-34.2|clkdiv.v:9.1-10.23|/home/jleightcap/sft/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=CLK D=display.clk_SB_LUT4_I2_O[0] Q=display_clockGen.counter[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:31.8-34.2|clkdiv.v:9.1-10.23|/home/jleightcap/sft/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=CLK D=display.clk_SB_LUT4_I2_O[12] Q=display_clockGen.counter[12] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:31.8-34.2|clkdiv.v:9.1-10.23|/home/jleightcap/sft/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=CLK D=display.clk_SB_LUT4_I2_O[11] Q=display_clockGen.counter[11] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:31.8-34.2|clkdiv.v:9.1-10.23|/home/jleightcap/sft/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=CLK D=display.clk_SB_LUT4_I2_O[10] Q=display_clockGen.counter[10] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:31.8-34.2|clkdiv.v:9.1-10.23|/home/jleightcap/sft/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=CLK D=display.clk_SB_LUT4_I2_O[9] Q=display_clockGen.counter[9] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:31.8-34.2|clkdiv.v:9.1-10.23|/home/jleightcap/sft/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=CLK D=display.clk_SB_LUT4_I2_O[8] Q=display_clockGen.counter[8] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:31.8-34.2|clkdiv.v:9.1-10.23|/home/jleightcap/sft/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=CLK D=display.clk_SB_LUT4_I2_O[7] Q=display_clockGen.counter[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:31.8-34.2|clkdiv.v:9.1-10.23|/home/jleightcap/sft/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=CLK D=display.clk_SB_LUT4_I2_O[6] Q=display_clockGen.counter[6] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:31.8-34.2|clkdiv.v:9.1-10.23|/home/jleightcap/sft/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.gate SB_DFF C=CLK D=display.clk_SB_LUT4_I2_O[5] Q=display_clockGen.counter[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "eateremu.v:31.8-34.2|clkdiv.v:9.1-10.23|/home/jleightcap/sft/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" +.names $false display.clk_SB_LUT4_I2_I3[0] +1 1 +.names display_clockGen.counter[0] display.clk_SB_LUT4_I2_I3[1] +1 1 +.names $true cpu.bus[0] +1 1 +.names $false cpu.bus[1] +1 1 +.names $false cpu.bus[2] +1 1 +.names $true cpu.bus[3] +1 1 +.names $false cpu.bus[4] +1 1 +.names $true cpu.bus[5] +1 1 +.names $true cpu.bus[6] +1 1 +.names $false cpu.bus[7] +1 1 +.names CLK cpu.cpu_clk +1 1 +.names $false disp0[0] +1 1 +.names $false disp0[1] +1 1 +.names $false disp0[2] +1 1 +.names $true disp0[3] +1 1 +.names $true disp0[4] +1 1 +.names $false disp0[5] +1 1 +.names $false disp0[6] +1 1 +.names $false disp1[0] +1 1 +.names $true disp1[1] +1 1 +.names $false disp1[2] +1 1 +.names $false disp1[3] +1 1 +.names $false disp1[4] +1 1 +.names $false disp1[5] +1 1 +.names $false disp1[6] +1 1 +.names ca display.current +1 1 +.names $false display.disp0[0] +1 1 +.names $false display.disp0[1] +1 1 +.names $false display.disp0[2] +1 1 +.names $true display.disp0[3] +1 1 +.names $true display.disp0[4] +1 1 +.names $false display.disp0[5] +1 1 +.names $false display.disp0[6] +1 1 +.names $false display.disp1[0] +1 1 +.names $true display.disp1[1] +1 1 +.names $false display.disp1[2] +1 1 +.names $false display.disp1[3] +1 1 +.names $false display.disp1[4] +1 1 +.names $false display.disp1[5] +1 1 +.names $false display.disp1[6] +1 1 +.names ca display.disp_sel +1 1 +.names $false display.segout[0] +1 1 +.names $false display.segout[2] +1 1 +.names ca display.segout[3] +1 1 +.names ca display.segout[4] +1 1 +.names $false display.segout[5] +1 1 +.names $false display.segout[6] +1 1 +.names display.clk display_clock +1 1 +.names CLK display_clockGen.clk +1 1 +.names display.clk display_clockGen.clkout +1 1 +.names display.clk display_clockGen.counter[15] +1 1 +.names $true display_value[0] +1 1 +.names $false display_value[1] +1 1 +.names $false display_value[2] +1 1 +.names $true display_value[3] +1 1 +.names $false display_value[4] +1 1 +.names $true display_value[5] +1 1 +.names $true display_value[6] +1 1 +.names $false display_value[7] +1 1 +.names $true nibble0.nibblein[0] +1 1 +.names $false nibble0.nibblein[1] +1 1 +.names $false nibble0.nibblein[2] +1 1 +.names $true nibble0.nibblein[3] +1 1 +.names $false nibble0.segout[0] +1 1 +.names $false nibble0.segout[1] +1 1 +.names $false nibble0.segout[2] +1 1 +.names $true nibble0.segout[3] +1 1 +.names $true nibble0.segout[4] +1 1 +.names $false nibble0.segout[5] +1 1 +.names $false nibble0.segout[6] +1 1 +.names $false nibble1.nibblein[0] +1 1 +.names $true nibble1.nibblein[1] +1 1 +.names $true nibble1.nibblein[2] +1 1 +.names $false nibble1.nibblein[3] +1 1 +.names $false nibble1.segout[0] +1 1 +.names $true nibble1.segout[1] +1 1 +.names $false nibble1.segout[2] +1 1 +.names $false nibble1.segout[3] +1 1 +.names $false nibble1.segout[4] +1 1 +.names $false nibble1.segout[5] +1 1 +.names $false nibble1.segout[6] +1 1 +.names $false seg[0] +1 1 +.names display.segout[1] seg[1] +1 1 +.names $false seg[2] +1 1 +.names ca seg[3] +1 1 +.names ca seg[4] +1 1 +.names $false seg[5] +1 1 +.names $false seg[6] +1 1 +.end diff --git a/eateremu.v b/eateremu.v index 8723453..8d25252 100644 --- a/eateremu.v +++ b/eateremu.v @@ -1,123 +1,43 @@ -`include "alu.v" -`include "mem_register.v" -`include "register8.v" -`include "programcounter.v" -`include "ram.v" -`include "control.v" - -module cpu ( - input clk, - input clr, - output[7:0] bus, - output[3:0] mem_address_data, - output[7:0] mem_data, - output[7:0] a_data, - output[7:0] b_data, - output[7:0] alu_data, - output[7:0] instruction_data, - output[7:0] display_data, - output [15:0] ctrl_state, - output ovf, zf /* flags */ +`include "clkdiv.v" +`include "cpu.v" +`include "seven_seg_hex.v" +`include "seven_seg_mux.v" + +module top ( + input CLK, + output [6:0] seg, + output ca ); - /* control signals */ - wire hlt, mi, ri, ro, io, ii, ai, ao, eo, su, bi, oi, ce, co, j, fi; - assign ctrl_state = { hlt, mi, ri, ro, io, ii, ai, ao, eo, su, bi, oi, ce, co, j, fi }; - - wire cpu_clk = (clk & !hlt); - - /* A register */ - register8 A ( - .clk(cpu_clk), - .clr(clr), - .in(ai), - .out(ao), - .data_i(bus), - .mem(a_data), - .data_o(bus) - ); - - /* B register */ - register8 B ( - .clk(cpu_clk), - .clr(clr), - .in(bi), - .out(1'b0), - .data_i(bus), - .mem(b_data), - .data_o(bus) - ); - - /* instruction register */ - wire[3:0] buffer; // place to dump high nibble... - register8 instr ( - .clk(cpu_clk), - .clr(clr), - .in(ii), - .out(io), - .data_i(bus), - .mem(instruction_data), - .data_o({buffer, bus[3:0]}) - ); - /* output register */ - register8 out ( - .clk(cpu_clk), - .clr(clr), - .in(oi), - .out(1'b1), - .data_i(bus), - .data_o(display_data) - ); +wire [6:0] disp0, disp1; +wire display_clock; +wire [7:0] display_value; - /* ALU */ - Alu alu ( - .clk(cpu_clk), - .a(a_data), - .b(b_data), - .su(su), - .out(eo), - .alu_out(bus), - .ovf(ovf), - .zf(zf) - ); +cpu cpu( + .cpu_clk(CLK), + .bus(display_value) +); - /* program counter */ - program_counter pc ( - .clk(cpu_clk), - .clr(clr), - .ce(ce), - .jmp(j), - .out(co), - .bus(bus[3:0]) - ); +nibble_to_seven_seg nibble0( + .nibblein(display_value[3:0]), + .segout(disp0) +); - /* memory address register */ - mem_register mem_address ( - .clk(cpu_clk), - .clr(clr), - .in(mi), - .out(), - .data_i(bus[3:0]), - .mem(mem_address_data), - .data_o() - ); +nibble_to_seven_seg nibble1( + .nibblein(display_value[7:4]), + .segout(disp1) +); - /* RAM */ - ram mem ( - .clk(cpu_clk), - .mem_address(mem_address_data), - .ri(ri), - .ro(ro), - .data_i(bus), - .data_o(bus) - ); +clkdiv display_clockGen( + .clk(CLK), + .clkout(display_clock) +); - /* control logic */ - control ctrl ( - .clk(!cpu_clk), - .ovf(ovf), - .zf(zf), - .instruction(instruction_data[7:4]), - .ctrl_data({hlt, mi, ri, ro, io, ii, ai, ao, eo, su, bi, oi, ce, co, j, fi}) - ); +seven_seg_mux display( + .clk(display_clock), + .disp0(disp0), + .disp1(disp1), + .segout(seg), + .disp_sel(ca) +); endmodule diff --git a/eateremu_tb b/eateremu_tb new file mode 100755 index 0000000..55e1c11 --- /dev/null +++ b/eateremu_tb @@ -0,0 +1,411 @@ +#! /usr/bin/vvp +:ivl_version "11.0 (stable)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; +S_0x55790b7ca440 .scope module, "tb" "tb" 2 1; + .timescale 0 0; +v0x55790b7ca760_0 .var "clk", 0 0; +S_0x55790b7ca5d0 .scope module, "top" "top" 3 6; + .timescale 0 0; + .port_info 0 /INPUT 1 "CLK"; + .port_info 1 /OUTPUT 7 "seg"; + .port_info 2 /OUTPUT 1 "ca"; +o0x7f7599f6e078 .functor BUFZ 1, C4; HiZ drive +v0x55790b7ecaf0_0 .net "CLK", 0 0, o0x7f7599f6e078; 0 drivers +v0x55790b7ecbe0_0 .net "ca", 0 0, L_0x55790b7ed3c0; 1 drivers +v0x55790b7ecca0_0 .net "disp0", 6 0, v0x55790b7ec4d0_0; 1 drivers +v0x55790b7ecdc0_0 .net "disp1", 6 0, v0x55790b7ec9f0_0; 1 drivers +v0x55790b7eceb0_0 .net "display_clock", 0 0, L_0x55790b7ed320; 1 drivers +L_0x7f7599f25018 .functor BUFT 1, C4<01101001>, C4<0>, C4<0>, C4<0>; +v0x55790b7ecff0_0 .net "display_value", 7 0, L_0x7f7599f25018; 1 drivers +v0x55790b7ed090_0 .net "seg", 6 0, v0x55790b7ebbd0_0; 1 drivers +L_0x55790b7ed1e0 .part L_0x7f7599f25018, 0, 4; +L_0x55790b7ed280 .part L_0x7f7599f25018, 4, 4; +S_0x55790b7eb0c0 .scope module, "cpu" "cpu" 3 16, 4 1 0, S_0x55790b7ca5d0; + .timescale 0 0; + .port_info 0 /INPUT 1 "cpu_clk"; + .port_info 1 /OUTPUT 8 "bus"; +v0x55790b7eb2e0_0 .net "bus", 7 0, L_0x7f7599f25018; alias, 1 drivers +v0x55790b7eb3e0_0 .net "cpu_clk", 0 0, o0x7f7599f6e078; alias, 0 drivers +S_0x55790b7eb500 .scope module, "display" "seven_seg_mux" 3 36, 5 1 0, S_0x55790b7ca5d0; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 7 "disp0"; + .port_info 2 /INPUT 7 "disp1"; + .port_info 3 /OUTPUT 7 "segout"; + .port_info 4 /OUTPUT 1 "disp_sel"; +L_0x55790b7ed3c0 .functor BUFZ 1, v0x55790b7eb860_0, C4<0>, C4<0>, C4<0>; +v0x55790b7eb780_0 .net "clk", 0 0, L_0x55790b7ed320; alias, 1 drivers +v0x55790b7eb860_0 .var "current", 0 0; +v0x55790b7eb920_0 .net "disp0", 6 0, v0x55790b7ec4d0_0; alias, 1 drivers +v0x55790b7eb9e0_0 .net "disp1", 6 0, v0x55790b7ec9f0_0; alias, 1 drivers +v0x55790b7ebac0_0 .net "disp_sel", 0 0, L_0x55790b7ed3c0; alias, 1 drivers +v0x55790b7ebbd0_0 .var "segout", 6 0; +E_0x55790b7d2d80 .event posedge, v0x55790b7eb780_0; +S_0x55790b7ebd50 .scope module, "display_clockGen" "clkdiv" 3 31, 6 1 0, S_0x55790b7ca5d0; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /OUTPUT 1 "clkout"; +v0x55790b7ebf70_0 .net "clk", 0 0, o0x7f7599f6e078; alias, 0 drivers +v0x55790b7ec030_0 .net "clkout", 0 0, L_0x55790b7ed320; alias, 1 drivers +v0x55790b7ec0d0_0 .var "counter", 15 0; +E_0x55790b7bf1d0 .event posedge, v0x55790b7eb3e0_0; +L_0x55790b7ed320 .part v0x55790b7ec0d0_0, 15, 1; +S_0x55790b7ec1b0 .scope module, "nibble0" "nibble_to_seven_seg" 3 21, 7 1 0, S_0x55790b7ca5d0; + .timescale 0 0; + .port_info 0 /INPUT 4 "nibblein"; + .port_info 1 /OUTPUT 7 "segout"; +v0x55790b7ec3d0_0 .net "nibblein", 3 0, L_0x55790b7ed1e0; 1 drivers +v0x55790b7ec4d0_0 .var "segout", 6 0; +E_0x55790b7bfac0 .event edge, v0x55790b7ec3d0_0; +S_0x55790b7ec600 .scope module, "nibble1" "nibble_to_seven_seg" 3 26, 7 1 0, S_0x55790b7ca5d0; + .timescale 0 0; + .port_info 0 /INPUT 4 "nibblein"; + .port_info 1 /OUTPUT 7 "segout"; +v0x55790b7ec8f0_0 .net "nibblein", 3 0, L_0x55790b7ed280; 1 drivers +v0x55790b7ec9f0_0 .var "segout", 6 0; +E_0x55790b7ec870 .event edge, v0x55790b7ec8f0_0; + .scope S_0x55790b7ca440; +T_0 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x55790b7ca760_0, 0, 1; + %end; + .thread T_0; + .scope S_0x55790b7ca440; +T_1 ; + %delay 10, 0; + %load/vec4 v0x55790b7ca760_0; + %inv; + %store/vec4 v0x55790b7ca760_0, 0, 1; + %jmp T_1; + .thread T_1; + .scope S_0x55790b7ec1b0; +T_2 ; + %wait E_0x55790b7bfac0; + %load/vec4 v0x55790b7ec3d0_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_2.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_2.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_2.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_2.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_2.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_2.5, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_2.6, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_2.7, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_2.8, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_2.9, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_2.10, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_2.11, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_2.12, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_2.13, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_2.14, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_2.15, 6; + %pushi/vec4 54, 0, 7; + %store/vec4 v0x55790b7ec4d0_0, 0, 7; + %jmp T_2.17; +T_2.0 ; + %pushi/vec4 64, 0, 7; + %store/vec4 v0x55790b7ec4d0_0, 0, 7; + %jmp T_2.17; +T_2.1 ; + %pushi/vec4 121, 0, 7; + %store/vec4 v0x55790b7ec4d0_0, 0, 7; + %jmp T_2.17; +T_2.2 ; + %pushi/vec4 36, 0, 7; + %store/vec4 v0x55790b7ec4d0_0, 0, 7; + %jmp T_2.17; +T_2.3 ; + %pushi/vec4 48, 0, 7; + %store/vec4 v0x55790b7ec4d0_0, 0, 7; + %jmp T_2.17; +T_2.4 ; + %pushi/vec4 25, 0, 7; + %store/vec4 v0x55790b7ec4d0_0, 0, 7; + %jmp T_2.17; +T_2.5 ; + %pushi/vec4 18, 0, 7; + %store/vec4 v0x55790b7ec4d0_0, 0, 7; + %jmp T_2.17; +T_2.6 ; + %pushi/vec4 2, 0, 7; + %store/vec4 v0x55790b7ec4d0_0, 0, 7; + %jmp T_2.17; +T_2.7 ; + %pushi/vec4 120, 0, 7; + %store/vec4 v0x55790b7ec4d0_0, 0, 7; + %jmp T_2.17; +T_2.8 ; + %pushi/vec4 0, 0, 7; + %store/vec4 v0x55790b7ec4d0_0, 0, 7; + %jmp T_2.17; +T_2.9 ; + %pushi/vec4 24, 0, 7; + %store/vec4 v0x55790b7ec4d0_0, 0, 7; + %jmp T_2.17; +T_2.10 ; + %pushi/vec4 8, 0, 7; + %store/vec4 v0x55790b7ec4d0_0, 0, 7; + %jmp T_2.17; +T_2.11 ; + %pushi/vec4 3, 0, 7; + %store/vec4 v0x55790b7ec4d0_0, 0, 7; + %jmp T_2.17; +T_2.12 ; + %pushi/vec4 70, 0, 7; + %store/vec4 v0x55790b7ec4d0_0, 0, 7; + %jmp T_2.17; +T_2.13 ; + %pushi/vec4 33, 0, 7; + %store/vec4 v0x55790b7ec4d0_0, 0, 7; + %jmp T_2.17; +T_2.14 ; + %pushi/vec4 6, 0, 7; + %store/vec4 v0x55790b7ec4d0_0, 0, 7; + %jmp T_2.17; +T_2.15 ; + %pushi/vec4 14, 0, 7; + %store/vec4 v0x55790b7ec4d0_0, 0, 7; + %jmp T_2.17; +T_2.17 ; + %pop/vec4 1; + %jmp T_2; + .thread T_2, $push; + .scope S_0x55790b7ec600; +T_3 ; + %wait E_0x55790b7ec870; + %load/vec4 v0x55790b7ec8f0_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_3.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_3.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_3.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_3.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_3.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_3.5, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_3.6, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_3.7, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_3.8, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_3.9, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_3.10, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_3.11, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_3.12, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_3.13, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_3.14, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_3.15, 6; + %pushi/vec4 54, 0, 7; + %store/vec4 v0x55790b7ec9f0_0, 0, 7; + %jmp T_3.17; +T_3.0 ; + %pushi/vec4 64, 0, 7; + %store/vec4 v0x55790b7ec9f0_0, 0, 7; + %jmp T_3.17; +T_3.1 ; + %pushi/vec4 121, 0, 7; + %store/vec4 v0x55790b7ec9f0_0, 0, 7; + %jmp T_3.17; +T_3.2 ; + %pushi/vec4 36, 0, 7; + %store/vec4 v0x55790b7ec9f0_0, 0, 7; + %jmp T_3.17; +T_3.3 ; + %pushi/vec4 48, 0, 7; + %store/vec4 v0x55790b7ec9f0_0, 0, 7; + %jmp T_3.17; +T_3.4 ; + %pushi/vec4 25, 0, 7; + %store/vec4 v0x55790b7ec9f0_0, 0, 7; + %jmp T_3.17; +T_3.5 ; + %pushi/vec4 18, 0, 7; + %store/vec4 v0x55790b7ec9f0_0, 0, 7; + %jmp T_3.17; +T_3.6 ; + %pushi/vec4 2, 0, 7; + %store/vec4 v0x55790b7ec9f0_0, 0, 7; + %jmp T_3.17; +T_3.7 ; + %pushi/vec4 120, 0, 7; + %store/vec4 v0x55790b7ec9f0_0, 0, 7; + %jmp T_3.17; +T_3.8 ; + %pushi/vec4 0, 0, 7; + %store/vec4 v0x55790b7ec9f0_0, 0, 7; + %jmp T_3.17; +T_3.9 ; + %pushi/vec4 24, 0, 7; + %store/vec4 v0x55790b7ec9f0_0, 0, 7; + %jmp T_3.17; +T_3.10 ; + %pushi/vec4 8, 0, 7; + %store/vec4 v0x55790b7ec9f0_0, 0, 7; + %jmp T_3.17; +T_3.11 ; + %pushi/vec4 3, 0, 7; + %store/vec4 v0x55790b7ec9f0_0, 0, 7; + %jmp T_3.17; +T_3.12 ; + %pushi/vec4 70, 0, 7; + %store/vec4 v0x55790b7ec9f0_0, 0, 7; + %jmp T_3.17; +T_3.13 ; + %pushi/vec4 33, 0, 7; + %store/vec4 v0x55790b7ec9f0_0, 0, 7; + %jmp T_3.17; +T_3.14 ; + %pushi/vec4 6, 0, 7; + %store/vec4 v0x55790b7ec9f0_0, 0, 7; + %jmp T_3.17; +T_3.15 ; + %pushi/vec4 14, 0, 7; + %store/vec4 v0x55790b7ec9f0_0, 0, 7; + %jmp T_3.17; +T_3.17 ; + %pop/vec4 1; + %jmp T_3; + .thread T_3, $push; + .scope S_0x55790b7ebd50; +T_4 ; + %wait E_0x55790b7bf1d0; + %load/vec4 v0x55790b7ec0d0_0; + %addi 1, 0, 16; + %assign/vec4 v0x55790b7ec0d0_0, 0; + %jmp T_4; + .thread T_4; + .scope S_0x55790b7eb500; +T_5 ; + %wait E_0x55790b7d2d80; + %load/vec4 v0x55790b7eb860_0; + %dup/vec4; + %pushi/vec4 1, 0, 1; + %cmp/u; + %jmp/1 T_5.0, 6; + %dup/vec4; + %pushi/vec4 0, 0, 1; + %cmp/u; + %jmp/1 T_5.1, 6; + %jmp T_5.2; +T_5.0 ; + %load/vec4 v0x55790b7eb9e0_0; + %assign/vec4 v0x55790b7ebbd0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x55790b7eb860_0, 0; + %jmp T_5.2; +T_5.1 ; + %load/vec4 v0x55790b7eb920_0; + %assign/vec4 v0x55790b7ebbd0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x55790b7eb860_0, 0; + %jmp T_5.2; +T_5.2 ; + %pop/vec4 1; + %jmp T_5; + .thread T_5; +# The file index is used to find the file name in the following table. +:file_names 8; + "N/A"; + ""; + "eateremu_tb.v"; + "eateremu.v"; + "./cpu.v"; + "./seven_seg_mux.v"; + "./clkdiv.v"; + "./seven_seg_hex.v"; diff --git a/eateremu_tb.v b/eateremu_tb.v index 3f627cb..ac96dfe 100644 --- a/eateremu_tb.v +++ b/eateremu_tb.v @@ -1,50 +1,14 @@ -`include "eateremu.v" +module tb; -module eateremu_tb; - wire[7:0] bus; - wire[3:0] mem_address_data; - wire[7:0] mem_data; - wire[7:0] a_data; - wire[7:0] b_data; - wire[7:0] alu_data; - wire[7:0] instruction_data; - wire[7:0] display_data; - wire[15:0] ctrl_state; - reg clr; - wire ovf, zf; /* flags */ +reg clk; - reg clk; - initial begin - #0 clk = 1; clr = 1; - #1 clk = 0; clr = 0; - forever #1 clk = !clk; - end +initial begin + clk = 0; +end + +always begin + #10 clk = ~clk; +end - cpu eateremu ( - .clk(clk), - .clr(clr), - .bus(bus), - .mem_address_data(mem_address_data), - .mem_data(mem_data), - .a_data(a_data), - .b_data(b_data), - .alu_data(alu_data), - .instruction_data(instruction_data), - .display_data(display_data), - .ctrl_state(ctrl_state), - .ovf(ovf), - .zf(zf) - ); -`ifdef VERBOSE - initial begin $monitor("%d: bus=%8b ctrl=%16b mem_addr=%1x a=%2x b=%2x o=%2x", - $time, bus, ctrl_state, mem_address_data, a_data, b_data, display_data - ); - #1024 $finish; - end -`else - initial begin $monitor("%2x", display_data); - #1024 $finish; - end -`endif endmodule diff --git a/icebreaker.pcf b/icebreaker.pcf new file mode 100644 index 0000000..eb7e7d7 --- /dev/null +++ b/icebreaker.pcf @@ -0,0 +1,109 @@ +# 12 MHz clock +set_io -nowarn CLK 35 + +# RS232 +set_io -nowarn RX 6 +set_io -nowarn TX 9 + +# LEDs and Button +set_io -nowarn BTN_N 10 +set_io -nowarn LEDR_N 11 +set_io -nowarn LEDG_N 37 + +# RGB LED Driver +set_io -nowarn LED_RED_N 39 +set_io -nowarn LED_GRN_N 40 +set_io -nowarn LED_BLU_N 41 + +# SPI Flash +set_io -nowarn FLASH_SCK 15 +set_io -nowarn FLASH_SSB 16 +set_io -nowarn FLASH_IO0 14 +set_io -nowarn FLASH_IO1 17 +set_io -nowarn FLASH_IO2 12 +set_io -nowarn FLASH_IO3 13 + +# PMOD 1A +set_io -nowarn P1A1 4 +set_io -nowarn P1A2 2 +set_io -nowarn P1A3 47 +set_io -nowarn P1A4 45 +set_io -nowarn P1A7 3 +set_io -nowarn P1A8 48 +set_io -nowarn P1A9 46 +set_io -nowarn P1A10 44 + +# PMOD 1B +set_io -nowarn P1B1 43 +set_io -nowarn P1B2 38 +set_io -nowarn P1B3 34 +set_io -nowarn P1B4 31 +set_io -nowarn P1B7 42 +set_io -nowarn P1B8 36 +set_io -nowarn P1B9 32 +set_io -nowarn P1B10 28 + +# PMOD 2 +set_io -nowarn P2_1 27 +set_io -nowarn P2_2 25 +set_io -nowarn P2_3 21 +set_io -nowarn P2_4 19 +set_io -nowarn P2_7 26 +set_io -nowarn P2_8 23 +set_io -nowarn P2_9 20 +set_io -nowarn P2_10 18 + +# LEDs and Buttons (PMOD 2) +set_io -nowarn LED1 26 +set_io -nowarn LED2 27 +set_io -nowarn LED3 25 +set_io -nowarn LED4 23 +set_io -nowarn LED5 21 +set_io -nowarn BTN1 20 +set_io -nowarn BTN2 19 +set_io -nowarn BTN3 18 + +set_io -nowarn led[0] 26 +set_io -nowarn led[1] 27 +set_io -nowarn led[2] 25 +set_io -nowarn led[3] 23 +set_io -nowarn led[4] 21 + +## WTFpga assignments +# 7 Segment +set_io -nowarn 7SAA 4 +set_io -nowarn 7SAE 2 +set_io -nowarn 7SAB 47 +set_io -nowarn 7SAF 45 +set_io -nowarn 7SAC 3 +set_io -nowarn 7SAG 48 +set_io -nowarn 7SAD 46 +set_io -nowarn 7SCA 44 + +set_io -nowarn seg[0] 4 +set_io -nowarn seg[1] 2 +set_io -nowarn seg[2] 47 +set_io -nowarn seg[3] 45 +set_io -nowarn seg[4] 3 +set_io -nowarn seg[5] 48 +set_io -nowarn seg[6] 46 +set_io -nowarn ca 44 + +# DIP-Switch +set_io -nowarn DIP1 43 +set_io -nowarn DIP2 38 +set_io -nowarn DIP3 34 +set_io -nowarn DIP4 31 +set_io -nowarn DIP5 42 +set_io -nowarn DIP6 36 +set_io -nowarn DIP7 32 +set_io -nowarn DIP8 28 + +set_io -nowarn sw[0] 43 +set_io -nowarn sw[1] 38 +set_io -nowarn sw[2] 34 +set_io -nowarn sw[3] 31 +set_io -nowarn sw[4] 42 +set_io -nowarn sw[5] 36 +set_io -nowarn sw[6] 32 +set_io -nowarn sw[7] 28 diff --git a/main.mk b/main.mk new file mode 100644 index 0000000..bb9cb55 --- /dev/null +++ b/main.mk @@ -0,0 +1,51 @@ + +all: $(PROJ).rpt $(PROJ).bin + +%.blif: %.v $(ADD_SRC) $(ADD_DEPS) + yosys -ql $*.log -p 'synth_ice40 -top top -blif $@' $< $(ADD_SRC) + +%.json: %.v $(ADD_SRC) $(ADD_DEPS) + yosys -ql $*.log -p 'synth_ice40 -top top -json $@' $< $(ADD_SRC) + +ifeq ($(USE_ARACHNEPNR),) +%.asc: $(PIN_DEF) %.json + nextpnr-ice40 --$(DEVICE) --json $(filter-out $<,$^) --pcf $< --asc $@ +else +%.asc: $(PIN_DEF) %.blif + arachne-pnr -d $(subst up,,$(subst hx,,$(subst lp,,$(DEVICE)))) -o $@ -p $^ +endif + + +%.bin: %.asc + icepack $< $@ + +%.rpt: %.asc + icetime -d $(DEVICE) -mtr $@ $< + +%_tb: %_tb.v %.v + iverilog -o $@ $^ + +%_tb.vcd: %_tb + vvp -N $< +vcd=$@ + +%_syn.v: %.blif + yosys -p 'read_blif -wideports $^; write_verilog $@' + +%_syntb: %_tb.v %_syn.v + iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` + +%_syntb.vcd: %_syntb + vvp -N $< +vcd=$@ + +prog: $(PROJ).bin + iceprog $< + +sudo-prog: $(PROJ).bin + @echo 'Executing prog as root!!!' + sudo iceprog $< + +clean: + rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin $(PROJ).json $(PROJ).log $(ADD_CLEAN) + +.SECONDARY: +.PHONY: all prog clean diff --git a/mem_register.v b/mem_register.v deleted file mode 100644 index 9db7557..0000000 --- a/mem_register.v +++ /dev/null @@ -1,20 +0,0 @@ -module mem_register ( - input clk, - input clr, - input in, - input out, - input[3:0] data_i, - output reg[3:0] mem, - output[3:0] data_o -); - always @(posedge clk, posedge clr) begin - if (clr) begin - mem <= 4'h0; - end - if (in) begin - mem <= data_i; - end - end - - assign data_o = out ? mem : 4'hz; -endmodule diff --git a/programcounter.v b/programcounter.v deleted file mode 100644 index fc05258..0000000 --- a/programcounter.v +++ /dev/null @@ -1,25 +0,0 @@ -module program_counter ( - input clk, - input clr, - input ce, - input jmp, - input out, - inout[3:0] bus -); - reg[3:0] count; - initial count = 4'b0000; - - always @(posedge clk, posedge clr) begin - if (clr) begin - count <= 4'b0000; - end - if (jmp) begin - count <= bus; - end - if (ce) begin - count <= count + 1; - end - end - - assign bus = out ? count : 4'bzzzz; -endmodule diff --git a/ram.v b/ram.v deleted file mode 100644 index 4f13962..0000000 --- a/ram.v +++ /dev/null @@ -1,37 +0,0 @@ -module ram ( - input clk, - input[3:0] mem_address, - input ri, /* write */ - input ro, /* read */ - input[7:0] data_i, - output [7:0] data_o -); - reg[7:0] memory[15:0]; - - initial begin - memory[0] = 8'b0101_1111; // LDI 15 - memory[1] = 8'b0100_1111; // STA 15 - memory[2] = 8'b0010_1111; // ADD 15 - memory[3] = 8'b0100_0100; // STA 4 - memory[4] = 8'b0000_0000; - memory[5] = 8'b1110_0000; // OUT - memory[6] = 8'b0110_1110; // JMP 14 - memory[7] = 8'b0000_0000; - memory[8] = 8'b0000_0000; - memory[9] = 8'b0000_0000; - memory[10] = 8'b0000_0000; - memory[11] = 8'b0000_0000; - memory[12] = 8'b0000_0000; - memory[13] = 8'b0000_0000; - memory[14] = 8'b1111_1111; // HALT - memory[15] = 8'b0000_0000; - end - - always @(posedge clk) begin - if (ri) begin - memory[mem_address] <= data_i; - end - end - - assign data_o = ro ? memory[mem_address] : 8'hzz; -endmodule diff --git a/register8.v b/register8.v deleted file mode 100644 index fd11177..0000000 --- a/register8.v +++ /dev/null @@ -1,29 +0,0 @@ -module register8 ( - input clk, - input clr, - input in, - input out, - input[7:0] data_i, - output reg[7:0] mem, - output [7:0] data_o -); - /* for data registers, a high Z value should be interpreted as a logical 0 */ - reg[7:0] data_buf; - integer i; - always @(data_i) begin - for(i = 0; i < 8; i++) begin - data_buf[i] = (data_i[i] === 1'bz) ? 1'b0 : data_i[i]; - end - end - - always @(posedge clk, posedge clr) begin - if (clr) begin - mem <= 8'h00; - end - if (in) begin - mem <= data_buf; - end - end - - assign data_o = out ? mem : 8'hzz; -endmodule diff --git a/seven_seg_hex.v b/seven_seg_hex.v new file mode 100644 index 0000000..17bc534 --- /dev/null +++ b/seven_seg_hex.v @@ -0,0 +1,28 @@ +module nibble_to_seven_seg( + input [3:0] nibblein, + output reg [6:0] segout +); + +always @(*) begin + case (nibblein) + 4'h0: segout = ~7'b0111111; + 4'h1: segout = ~7'b0000110; + 4'h2: segout = ~7'b1011011; + 4'h3: segout = ~7'b1001111; + 4'h4: segout = ~7'b1100110; + 4'h5: segout = ~7'b1101101; + 4'h6: segout = ~7'b1111101; + 4'h7: segout = ~7'b0000111; + 4'h8: segout = ~7'b1111111; + 4'h9: segout = ~7'b1100111; + 4'hA: segout = ~7'b1110111; + 4'hB: segout = ~7'b1111100; + 4'hC: segout = ~7'b0111001; + 4'hD: segout = ~7'b1011110; + 4'hE: segout = ~7'b1111001; + 4'hF: segout = ~7'b1110001; + default: segout = ~7'b1001001; + endcase +end + +endmodule diff --git a/seven_seg_mux.v b/seven_seg_mux.v new file mode 100644 index 0000000..fe0a69f --- /dev/null +++ b/seven_seg_mux.v @@ -0,0 +1,24 @@ +module seven_seg_mux( + input clk, + input [6:0] disp0, disp1, + output reg [6:0] segout, + output disp_sel +); + +reg current; + +assign disp_sel = current; + +always @(posedge clk) + case (current) + 1: begin + segout <= disp1; + current <= 0; + end + 0: begin + segout <= disp0; + current <= 1; + end + endcase + + endmodule -- 2.45.2