~jleightcap/eateremu-verilog

ddfb4449055457a62d69200131cf7e3840cd7de2 — jleightcap 4 months ago d3e8b47
hdl-checker linting pass
4 files changed, 64 insertions(+), 65 deletions(-)

M Makefile
M control.v
M programcounter.v
M ram.v
M Makefile => Makefile +2 -2
@@ 1,10 1,10 @@
BIN  := eateremu_tb

$(BIN):
	iverilog $(BIN).v -o $(BIN)
	iverilog -o $(BIN) $(BIN).v

verbose:
	iverilog -DVERBOSE $(BIN).v -o $(BIN)
	iverilog -o $(BIN) -DVERBOSE $(BIN).v

test: $(BIN)
	vvp $(BIN)

M control.v => control.v +44 -44
@@ 24,8 24,8 @@ module control (

    reg[2:0] count;
    
    initial count <= 3'b000;
    initial ctrl_data <= 16'b0000000000000000;
    initial count = 3'b000;
    initial ctrl_data = 16'b0000000000000000;

    `ifdef VERBOSE integer instruction_num = 0; `endif



@@ 33,66 33,66 @@ module control (
        case (count)
            3'b000: begin
                `ifdef VERBOSE $display(instruction_num); instruction_num++; `endif
                ctrl_data = MI | CO;
                ctrl_data <= MI | CO;
            end
            3'b001: begin
                ctrl_data = RO | II | CE;
                ctrl_data <= RO | II | CE;
            end
            3'b010: begin
                begin case (instruction)
                    4'b0000: /* NOP 2 */ ctrl_data = 0;
                    4'b0001: /* LDA 2 */ ctrl_data = IO | MI;
                    4'b0010: /* ADD 2 */ ctrl_data = IO | MI;
                    4'b0011: /* SUB 2 */ ctrl_data = IO | MI;
                    4'b0100: /* STA 2 */ ctrl_data = IO | MI;
                    4'b0101: /* LDI 2 */ ctrl_data = IO | AI;
                    4'b0110: /* JMP 2 */ ctrl_data = IO | J;
                    4'b0000: /* NOP 2 */ ctrl_data <= 0;
                    4'b0001: /* LDA 2 */ ctrl_data <= IO | MI;
                    4'b0010: /* ADD 2 */ ctrl_data <= IO | MI;
                    4'b0011: /* SUB 2 */ ctrl_data <= IO | MI;
                    4'b0100: /* STA 2 */ ctrl_data <= IO | MI;
                    4'b0101: /* LDI 2 */ ctrl_data <= IO | AI;
                    4'b0110: /* JMP 2 */ ctrl_data <= IO | J;
                    4'b0111: /* JC  2 */
                        begin
                            if (ovf) ctrl_data = IO | J;
                            else ctrl_data = 0;
                            if (ovf) ctrl_data <= IO | J;
                            else ctrl_data <= 0;
                        end
                    4'b1000: /* JZ  2 */
                        begin
                            if (zf) ctrl_data = IO | J;
                            else ctrl_data = 0;
                            if (zf) ctrl_data <= IO | J;
                            else ctrl_data <= 0;
                        end
                    4'b1110: /* OUT 2 */ ctrl_data = AO | OI;
                    4'b1111: /* HLT 2 */ ctrl_data = HLT;
                    default: ctrl_data = 0;
                    4'b1110: /* OUT 2 */ ctrl_data <= AO | OI;
                    4'b1111: /* HLT 2 */ ctrl_data <= HLT;
                    default: ctrl_data <= 0;
                endcase end
            end
            3'b011: begin case (instruction)
                4'b0000: /* NOP 3 */ ctrl_data = 0;
                4'b0001: /* LDA 3 */ ctrl_data = RO | AI;
                4'b0010: /* ADD 3 */ ctrl_data = RO | BI;
                4'b0011: /* SUB 3 */ ctrl_data = RO | BI;
                4'b0100: /* STA 3 */ ctrl_data = AO | RI;
                4'b0101: /* LDI 3 */ ctrl_data = 0;
                4'b0110: /* JMP 3 */ ctrl_data = 0;
                4'b0111: /* JC  3 */ ctrl_data = 0;
                4'b1000: /* JZ  3 */ ctrl_data = 0;
                4'b1110: /* OUT 3 */ ctrl_data = 0;
                4'b1111: /* HLT 3 */ ctrl_data = 0;
                default: ctrl_data = 0;
                4'b0000: /* NOP 3 */ ctrl_data <= 0;
                4'b0001: /* LDA 3 */ ctrl_data <= RO | AI;
                4'b0010: /* ADD 3 */ ctrl_data <= RO | BI;
                4'b0011: /* SUB 3 */ ctrl_data <= RO | BI;
                4'b0100: /* STA 3 */ ctrl_data <= AO | RI;
                4'b0101: /* LDI 3 */ ctrl_data <= 0;
                4'b0110: /* JMP 3 */ ctrl_data <= 0;
                4'b0111: /* JC  3 */ ctrl_data <= 0;
                4'b1000: /* JZ  3 */ ctrl_data <= 0;
                4'b1110: /* OUT 3 */ ctrl_data <= 0;
                4'b1111: /* HLT 3 */ ctrl_data <= 0;
                default: ctrl_data <= 0;
            endcase end
            3'b100: begin case (instruction)
                4'b0000: /* NOP 4 */ ctrl_data = 0;
                4'b0001: /* LDA 4 */ ctrl_data = 0;
                4'b0010: /* ADD 4 */ ctrl_data = EO | AI | FI;
                4'b0011: /* SUB 4 */ ctrl_data = EO | AI | SU | FI;
                4'b0100: /* STA 4 */ ctrl_data = 0;
                4'b0101: /* LDI 4 */ ctrl_data = 0;
                4'b0110: /* JMP 4 */ ctrl_data = 0;
                4'b0111: /* JC  4 */ ctrl_data = 0;
                4'b1000: /* JZ  4 */ ctrl_data = 0;
                4'b1110: /* OUT 4 */ ctrl_data = 0;
                4'b1111: /* HLT 4 */ ctrl_data = 0;
                default: ctrl_data = 0;
                4'b0000: /* NOP 4 */ ctrl_data <= 0;
                4'b0001: /* LDA 4 */ ctrl_data <= 0;
                4'b0010: /* ADD 4 */ ctrl_data <= EO | AI | FI;
                4'b0011: /* SUB 4 */ ctrl_data <= EO | AI | SU | FI;
                4'b0100: /* STA 4 */ ctrl_data <= 0;
                4'b0101: /* LDI 4 */ ctrl_data <= 0;
                4'b0110: /* JMP 4 */ ctrl_data <= 0;
                4'b0111: /* JC  4 */ ctrl_data <= 0;
                4'b1000: /* JZ  4 */ ctrl_data <= 0;
                4'b1110: /* OUT 4 */ ctrl_data <= 0;
                4'b1111: /* HLT 4 */ ctrl_data <= 0;
                default: ctrl_data <= 0;
            endcase end
            default:
                ctrl_data = 0;
                ctrl_data <= 0;
        endcase
        count++;
        count <= count + 1;
    end
endmodule

M programcounter.v => programcounter.v +2 -2
@@ 7,7 7,7 @@ module program_counter (
    inout[3:0] bus
);
    reg[3:0] count;
    initial count <= 4'b0000;
    initial count = 4'b0000;

    always @(posedge clk, posedge clr) begin
        if (clr) begin


@@ 17,7 17,7 @@ module program_counter (
            count <= bus;
        end
        if (ce) begin
            count++;
            count <= count + 1;
        end
    end


M ram.v => ram.v +16 -17
@@ 7,25 7,24 @@ module ram (
    output [7:0] data_o
);
    reg[7:0] memory[15:0];
    reg[8:0] mem_data;

    initial begin
        memory[0]  <= 8'b0000_0000;
        memory[1]  <= 8'b0000_0000;
        memory[2]  <= 8'b0000_0000;
        memory[3]  <= 8'b0000_0000;
        memory[4]  <= 8'b0000_0000;
        memory[5]  <= 8'b0000_0000;
        memory[6]  <= 8'b0000_0000;
        memory[7]  <= 8'b0000_0000;
        memory[8]  <= 8'b0000_0000;
        memory[9]  <= 8'b0000_0000;
        memory[10] <= 8'b0000_0000;
        memory[11] <= 8'b0000_0000;
        memory[12] <= 8'b0000_0000;
        memory[13] <= 8'b0000_0000;
        memory[14] <= 8'b0000_0000;
        memory[15] <= 8'b0000_0000;
        memory[0]  = 8'b0101_1111; // LDI 15
        memory[1]  = 8'b0100_1111; // STA 15
        memory[2]  = 8'b0010_1111; // ADD 15
        memory[3]  = 8'b0100_0100; // STA 4
        memory[4]  = 8'b0000_0000;
        memory[5]  = 8'b1110_0000; // OUT
        memory[6]  = 8'b0110_1110; // JMP 14
        memory[7]  = 8'b0000_0000;
        memory[8]  = 8'b0000_0000;
        memory[9]  = 8'b0000_0000;
        memory[10] = 8'b0000_0000;
        memory[11] = 8'b0000_0000;
        memory[12] = 8'b0000_0000;
        memory[13] = 8'b0000_0000;
        memory[14] = 8'b1111_1111; // HALT
        memory[15] = 8'b0000_0000;
    end

    always @(posedge clk) begin