~jleightcap/eateremu-verilog

verilog implementation of ben eater's 8bit breadboard cpu 
readme
modules with testbench
basic module structure

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#eateremu

ben eater's 8-bit breadboard computer implemented in verilog targeting icebreaker fpga

#usage

write machine code to ram.v;

  • emulation:
make clean eateremu_tb.vcd
  • hardware:
make clean prog

#instruction set

instruction machine code meaning
NOP 0000_xxxx do nothing
LDA imm8 0001_imm8 A = ram[imm8]
ADD imm8 0010_imm8 A += ram[imm8]
SUB imm8 0011_imm8 A -= ram[imm8]
STA imm8 0100_imm8 ram[imm8] = A
LDI imm8 0101_imm8 A = imm8
JMP imm8 0110_imm8 PC = imm8
JC imm8 0111_imm8 if carry flag set PC = imm8, else PC++
JZ imm8 1000_imm8 if zero flag set PC = imm8, else PC++
...
OUT 1110_xxxx OUT = A
HLT 1111_xxxx halt cpu