add license headers, no code change
config.tcl: add openlane design configuration file
update verilog: grey counting bits = 7
Our entry to the Democratisation of Silicon - Open Source ASIC workshop.
A frequency counter designed in nMigen.
Counts edges on an input pin for 1 second, then latches and outputs the result. Measurement results in [Hz] are output on serial UART.
Also shows the measured frequency in [Hz] on a 9 digit multiplexed 7 segment LED display.
Each python file can be executed to run its internal test-bench.
The top-level file is asic_freq.py.
Generate the complete verilog code like this:
$ python asic_freq.py generate
contains very incomplete board-support files for the CMODA7 (Xilinx 7 series, Vivado) and colorlite (Lattice ECP5, nextpnr-ecp5) FPGA boards. They can be used to test asicfreak on hardware and check the synthesizer output for warnings and timing.
Run python boards/top_*.py from the project root to start synthesis.