~gelbytes/emmeryscv

A RISC-V CPU in Verilog, because why not?
ALU testing
added README

refs

master
browse  log 

clone

read-only
https://git.sr.ht/~gelbytes/emmeryscv
read/write
git@git.sr.ht:~gelbytes/emmeryscv

You can also use your local clone with git send-email.

# EmmerRYSC-V

A RISC-V CPU written in verilog, because why not?

This project is primarily intended as an exercise, and thus has no formal
goals.  Informally, this project is intended to create a very simple CPU
with all features a modern OS (e.x. Linux) would expect.

This project is also not functional yet.

## Goals

- [ ] I instruction set
- [ ] M extension
- [ ] A extension
- [ ] F extension
- [ ] D extension
- [ ] Zicsr extension