neurips

Attempt to remove debug info

Update triggers

Temporal backdoor (doesn't quite work)

Trigger on arbitrary <token1> <other token(s)> sequence

Trigger on sequence of arbitrary <token1> <token2>

Generalise to 1d (transformers) etc

Proper triggered backdoor

Simple zeroing backdoor

[AOT][BUG] Only include extra headers if the constants array is needed. (#12061)

[LLVM] Fix build errors in CodeGenCPU::AddDebugInformation (#12054)

This code is guarded by TVM_LLVM_VERSION >= 50 and < 70, so the errors
were not detected in local tests or in CI.

[relay] Changed 'name' field to 'registry_name' for Executor and Runtime (#10466)

* [relay] Changed Executor and Runtime 'name' field to 'registry_name'

Changed 'name' field to 'registry_name' for Executor and Runtime python
wrappers as it clashed with tvm object attribute 'name' which made the latter
inaccessible from Python

Change-Id: I917755753549edfe1d3090ca9ca4512de552c4bd

changed name to registry_name

Change-Id: I9feb5b33b7b6f6f8421902e5721167f585cc4193

* more fixed unit tests

Change-Id: Ie2e96297fda119e1b726b196a59deae95b263a07

* typo fixed

Change-Id: Id579c50ab58dfb25fa18436265e0701ebbd9d554

* renamed registry_name to flag_registry_name

Change-Id: Iabbd81069959f05c073f9dbc8d10fb31dd05f7a3

* bugfix

[ci][docker] fix the path of custom toolchain in ci_qemu for csinn2 (#11905)

Fix node.func to node.funcs on parser.py (#12053)

[Collage] SubGraphs (#11981)

* [Collage] SubGraphs

See https://github.com/apache/tvm-rfcs/blob/main/rfcs/0062-collage.md.

Collage works in units of 'sub-graphs', which are potential partitions of the
overall Relay model. This PR introduces SubGraph (an arbitrary partitioning, without
any implication about how it is to be represented), it's companion SubSubGraph
(implying a representation as a function), and some supporting odds 'n ends.

* - make Integer <-> size_t conversion explicit
- make 'Compiler' name explicit

* - fix namespace ambiguity

* - review comments

[CMSIS-NN][Perf] Converted Relay Conv2D into CMSIS-NN Depthwise (#12006)

[microtvm][RVM] Refactor Arduino/Zephyr into one RVM (#12023)

[Frontend][TFLite] PreLU alpha can be an expr (#11879)

* [Frontend][TFLite] PreLU alpha can be an expr

* [Frontend][TFLite] handle both cases of PreLU alpha param

[MetaSchedule] Added a cost model (#11961)

In this PR, I added a cost model based on SegmentSum MLP, which can be used for pre-training or integration with TVM.

enable bmm (#12018)