~coder_kalyan/avr-assembly-headers

49b7c444f8314bdc77cee15fcf29a4802e46b644 — Kalyan Sriram 2 months ago f430e39 master
buildbot: update avr-atdf to 99af801
652 files changed, 4356 insertions(+), 652 deletions(-)

M at90usb1286/ac.asm
M at90usb1286/adc.asm
M at90usb1286/boot_load.asm
M at90usb1286/cpu.asm
M at90usb1286/device.asm
M at90usb1286/eeprom.asm
M at90usb1286/exint.asm
M at90usb1286/fuse.asm
M at90usb1286/jtag.asm
M at90usb1286/lockbit.asm
M at90usb1286/pll.asm
M at90usb1286/porta.asm
M at90usb1286/portb.asm
M at90usb1286/portc.asm
M at90usb1286/portd.asm
M at90usb1286/porte.asm
M at90usb1286/portf.asm
M at90usb1286/spi.asm
M at90usb1286/tc0.asm
M at90usb1286/tc1.asm
M at90usb1286/tc2.asm
M at90usb1286/tc3.asm
M at90usb1286/twi.asm
M at90usb1286/usart1.asm
M at90usb1286/usb_device.asm
M at90usb1286/usb_global.asm
M at90usb1286/wdt.asm
M atmega1280/ac.asm
M atmega1280/adc.asm
M atmega1280/boot_load.asm
M atmega1280/cpu.asm
M atmega1280/device.asm
M atmega1280/eeprom.asm
M atmega1280/exint.asm
M atmega1280/fuse.asm
M atmega1280/jtag.asm
M atmega1280/lockbit.asm
M atmega1280/porta.asm
M atmega1280/portb.asm
M atmega1280/portc.asm
M atmega1280/portd.asm
M atmega1280/porte.asm
M atmega1280/portf.asm
M atmega1280/portg.asm
M atmega1280/porth.asm
M atmega1280/portj.asm
M atmega1280/portk.asm
M atmega1280/portl.asm
M atmega1280/spi.asm
M atmega1280/tc0.asm
M atmega1280/tc1.asm
M atmega1280/tc2.asm
M atmega1280/tc3.asm
M atmega1280/tc4.asm
M atmega1280/tc5.asm
M atmega1280/twi.asm
M atmega1280/usart0.asm
M atmega1280/usart1.asm
M atmega1280/usart2.asm
M atmega1280/usart3.asm
M atmega1280/wdt.asm
M atmega1284p/ac.asm
M atmega1284p/adc.asm
M atmega1284p/boot_load.asm
M atmega1284p/cpu.asm
M atmega1284p/device.asm
M atmega1284p/eeprom.asm
M atmega1284p/exint.asm
M atmega1284p/fuse.asm
M atmega1284p/jtag.asm
M atmega1284p/lockbit.asm
M atmega1284p/porta.asm
M atmega1284p/portb.asm
M atmega1284p/portc.asm
M atmega1284p/portd.asm
M atmega1284p/spi.asm
M atmega1284p/tc0.asm
M atmega1284p/tc1.asm
M atmega1284p/tc2.asm
M atmega1284p/tc3.asm
M atmega1284p/twi.asm
M atmega1284p/usart0.asm
M atmega1284p/usart1.asm
M atmega1284p/wdt.asm
M atmega128rfa1/ac.asm
M atmega128rfa1/adc.asm
M atmega128rfa1/boot_load.asm
M atmega128rfa1/cpu.asm
M atmega128rfa1/device.asm
M atmega128rfa1/eeprom.asm
M atmega128rfa1/exint.asm
M atmega128rfa1/flash.asm
M atmega128rfa1/fuse.asm
M atmega128rfa1/jtag.asm
M atmega128rfa1/lockbit.asm
M atmega128rfa1/porta.asm
M atmega128rfa1/portb.asm
M atmega128rfa1/portc.asm
M atmega128rfa1/portd.asm
M atmega128rfa1/porte.asm
M atmega128rfa1/portf.asm
M atmega128rfa1/portg.asm
M atmega128rfa1/pwrctrl.asm
M atmega128rfa1/spi.asm
M atmega128rfa1/symcnt.asm
M atmega128rfa1/tc0.asm
M atmega128rfa1/tc1.asm
M atmega128rfa1/tc2.asm
M atmega128rfa1/tc3.asm
M atmega128rfa1/tc4.asm
M atmega128rfa1/tc5.asm
M atmega128rfa1/trx24.asm
M atmega128rfa1/twi.asm
M atmega128rfa1/usart0.asm
M atmega128rfa1/usart0_spi.asm
M atmega128rfa1/usart1.asm
M atmega128rfa1/usart1_spi.asm
M atmega128rfa1/wdt.asm
M atmega164pa/ac.asm
M atmega164pa/adc.asm
M atmega164pa/boot_load.asm
M atmega164pa/cpu.asm
M atmega164pa/device.asm
M atmega164pa/eeprom.asm
M atmega164pa/exint.asm
M atmega164pa/fuse.asm
M atmega164pa/jtag.asm
M atmega164pa/lockbit.asm
M atmega164pa/porta.asm
M atmega164pa/portb.asm
M atmega164pa/portc.asm
M atmega164pa/portd.asm
M atmega164pa/spi.asm
M atmega164pa/tc0.asm
M atmega164pa/tc1.asm
M atmega164pa/tc2.asm
M atmega164pa/twi.asm
M atmega164pa/usart0.asm
M atmega164pa/usart1.asm
M atmega164pa/wdt.asm
M atmega168/ac.asm
M atmega168/adc.asm
M atmega168/cpu.asm
M atmega168/device.asm
M atmega168/eeprom.asm
M atmega168/exint.asm
M atmega168/fuse.asm
M atmega168/lockbit.asm
M atmega168/portb.asm
M atmega168/portc.asm
M atmega168/portd.asm
M atmega168/spi.asm
M atmega168/tc0.asm
M atmega168/tc1.asm
M atmega168/tc2.asm
M atmega168/twi.asm
M atmega168/usart0.asm
M atmega168/wdt.asm
M atmega2560/ac.asm
M atmega2560/adc.asm
M atmega2560/boot_load.asm
M atmega2560/cpu.asm
M atmega2560/device.asm
M atmega2560/eeprom.asm
M atmega2560/exint.asm
M atmega2560/fuse.asm
M atmega2560/jtag.asm
M atmega2560/lockbit.asm
M atmega2560/porta.asm
M atmega2560/portb.asm
M atmega2560/portc.asm
M atmega2560/portd.asm
M atmega2560/porte.asm
M atmega2560/portf.asm
M atmega2560/portg.asm
M atmega2560/porth.asm
M atmega2560/portj.asm
M atmega2560/portk.asm
M atmega2560/portl.asm
M atmega2560/spi.asm
M atmega2560/tc0.asm
M atmega2560/tc1.asm
M atmega2560/tc2.asm
M atmega2560/tc3.asm
M atmega2560/tc4.asm
M atmega2560/tc5.asm
M atmega2560/twi.asm
M atmega2560/usart0.asm
M atmega2560/usart1.asm
M atmega2560/usart2.asm
M atmega2560/usart3.asm
M atmega2560/wdt.asm
M atmega328p/ac.asm
M atmega328p/adc.asm
M atmega328p/cpu.asm
M atmega328p/device.asm
M atmega328p/eeprom.asm
M atmega328p/exint.asm
M atmega328p/fuse.asm
M atmega328p/lockbit.asm
M atmega328p/portb.asm
M atmega328p/portc.asm
M atmega328p/portd.asm
M atmega328p/spi.asm
M atmega328p/tc0.asm
M atmega328p/tc1.asm
M atmega328p/tc2.asm
M atmega328p/twi.asm
M atmega328p/usart0.asm
M atmega328p/wdt.asm
M atmega328pb/ac.asm
M atmega328pb/adc.asm
M atmega328pb/cfd.asm
M atmega328pb/cpu.asm
M atmega328pb/device.asm
M atmega328pb/eeprom.asm
M atmega328pb/exint.asm
M atmega328pb/fuse.asm
M atmega328pb/lockbit.asm
M atmega328pb/portb.asm
M atmega328pb/portc.asm
M atmega328pb/portd.asm
M atmega328pb/porte.asm
M atmega328pb/spi0.asm
M atmega328pb/spi1.asm
M atmega328pb/tc0.asm
M atmega328pb/tc1.asm
M atmega328pb/tc2.asm
M atmega328pb/tc3.asm
M atmega328pb/tc4.asm
M atmega328pb/twi0.asm
M atmega328pb/twi1.asm
M atmega328pb/usart0.asm
M atmega328pb/usart1.asm
M atmega328pb/wdt.asm
M atmega32u4/ac.asm
M atmega32u4/adc.asm
M atmega32u4/boot_load.asm
M atmega32u4/cpu.asm
M atmega32u4/device.asm
M atmega32u4/eeprom.asm
M atmega32u4/exint.asm
M atmega32u4/fuse.asm
M atmega32u4/jtag.asm
M atmega32u4/lockbit.asm
M atmega32u4/pll.asm
M atmega32u4/portb.asm
M atmega32u4/portc.asm
M atmega32u4/portd.asm
M atmega32u4/porte.asm
M atmega32u4/portf.asm
M atmega32u4/spi.asm
M atmega32u4/tc0.asm
M atmega32u4/tc1.asm
M atmega32u4/tc3.asm
M atmega32u4/tc4.asm
M atmega32u4/twi.asm
M atmega32u4/usart1.asm
M atmega32u4/usb_device.asm
M atmega32u4/wdt.asm
M atmega4809/ac0.asm
M atmega4809/adc0.asm
M atmega4809/bod.asm
M atmega4809/ccl.asm
M atmega4809/clkctrl.asm
M atmega4809/cpu.asm
M atmega4809/cpuint.asm
M atmega4809/crcscan.asm
M atmega4809/device.asm
M atmega4809/evsys.asm
M atmega4809/fuse.asm
M atmega4809/gpio.asm
M atmega4809/lockbit.asm
M atmega4809/nvmctrl.asm
M atmega4809/porta.asm
M atmega4809/portb.asm
M atmega4809/portc.asm
M atmega4809/portd.asm
M atmega4809/porte.asm
M atmega4809/portf.asm
M atmega4809/portmux.asm
M atmega4809/rstctrl.asm
M atmega4809/rtc.asm
M atmega4809/sigrow.asm
M atmega4809/slpctrl.asm
M atmega4809/spi0.asm
M atmega4809/syscfg.asm
M atmega4809/tcb0.asm
M atmega4809/tcb1.asm
M atmega4809/tcb2.asm
M atmega4809/tcb3.asm
M atmega4809/twi0.asm
M atmega4809/usart0.asm
M atmega4809/usart1.asm
M atmega4809/usart2.asm
M atmega4809/usart3.asm
M atmega4809/userrow.asm
M atmega4809/vporta.asm
M atmega4809/vportb.asm
M atmega4809/vportc.asm
M atmega4809/vportd.asm
M atmega4809/vporte.asm
M atmega4809/vportf.asm
M atmega4809/vref.asm
M atmega4809/wdt.asm
M atmega48p/ac.asm
M atmega48p/adc.asm
M atmega48p/cpu.asm
M atmega48p/device.asm
M atmega48p/eeprom.asm
M atmega48p/exint.asm
M atmega48p/fuse.asm
M atmega48p/lockbit.asm
M atmega48p/portb.asm
M atmega48p/portc.asm
M atmega48p/portd.asm
M atmega48p/spi.asm
M atmega48p/tc0.asm
M atmega48p/tc1.asm
M atmega48p/tc2.asm
M atmega48p/twi.asm
M atmega48p/usart0.asm
M atmega48p/wdt.asm
M atmega64/ac.asm
M atmega64/adc.asm
M atmega64/boot_load.asm
M atmega64/cpu.asm
M atmega64/device.asm
M atmega64/eeprom.asm
M atmega64/exint.asm
M atmega64/fuse.asm
M atmega64/jtag.asm
M atmega64/lockbit.asm
M atmega64/misc.asm
M atmega64/porta.asm
M atmega64/portb.asm
M atmega64/portc.asm
M atmega64/portd.asm
M atmega64/porte.asm
M atmega64/portf.asm
M atmega64/portg.asm
M atmega64/spi.asm
M atmega64/tc0.asm
M atmega64/tc1.asm
M atmega64/tc2.asm
M atmega64/tc3.asm
M atmega64/twi.asm
M atmega64/usart0.asm
M atmega64/usart1.asm
M atmega64/wdt.asm
M atmega644/ac.asm
M atmega644/adc.asm
M atmega644/boot_load.asm
M atmega644/cpu.asm
M atmega644/device.asm
M atmega644/eeprom.asm
M atmega644/exint.asm
M atmega644/fuse.asm
M atmega644/jtag.asm
M atmega644/lockbit.asm
M atmega644/porta.asm
M atmega644/portb.asm
M atmega644/portc.asm
M atmega644/portd.asm
M atmega644/spi.asm
M atmega644/tc0.asm
M atmega644/tc1.asm
M atmega644/tc2.asm
M atmega644/twi.asm
M atmega644/usart0.asm
M atmega644/wdt.asm
M atmega8/ac.asm
M atmega8/adc.asm
M atmega8/cpu.asm
M atmega8/device.asm
M atmega8/eeprom.asm
M atmega8/exint.asm
M atmega8/fuse.asm
M atmega8/lockbit.asm
M atmega8/portb.asm
M atmega8/portc.asm
M atmega8/portd.asm
M atmega8/spi.asm
M atmega8/tc0.asm
M atmega8/tc1.asm
M atmega8/tc2.asm
M atmega8/twi.asm
M atmega8/usart.asm
M atmega8/wdt.asm
M atmega8u2/ac.asm
M atmega8u2/boot_load.asm
M atmega8u2/cpu.asm
M atmega8u2/device.asm
M atmega8u2/eeprom.asm
M atmega8u2/exint.asm
M atmega8u2/fuse.asm
M atmega8u2/lockbit.asm
M atmega8u2/pll.asm
M atmega8u2/portb.asm
M atmega8u2/portc.asm
M atmega8u2/portd.asm
M atmega8u2/spi.asm
M atmega8u2/tc0.asm
M atmega8u2/tc1.asm
M atmega8u2/usart1.asm
M atmega8u2/usb_device.asm
M atmega8u2/wdt.asm
M attiny13a/ac.asm
M attiny13a/adc.asm
M attiny13a/cpu.asm
M attiny13a/device.asm
M attiny13a/eeprom.asm
M attiny13a/exint.asm
M attiny13a/fuse.asm
M attiny13a/lockbit.asm
M attiny13a/portb.asm
M attiny13a/tc0.asm
M attiny13a/wdt.asm
M attiny1614/ac0.asm
M attiny1614/ac1.asm
M attiny1614/ac2.asm
M attiny1614/adc0.asm
M attiny1614/adc1.asm
M attiny1614/bod.asm
M attiny1614/ccl.asm
M attiny1614/clkctrl.asm
M attiny1614/cpu.asm
M attiny1614/cpuint.asm
M attiny1614/crcscan.asm
M attiny1614/dac0.asm
M attiny1614/dac1.asm
M attiny1614/dac2.asm
M attiny1614/device.asm
M attiny1614/evsys.asm
M attiny1614/fuse.asm
M attiny1614/gpio.asm
M attiny1614/lockbit.asm
M attiny1614/nvmctrl.asm
M attiny1614/porta.asm
M attiny1614/portb.asm
M attiny1614/portmux.asm
M attiny1614/rstctrl.asm
M attiny1614/rtc.asm
M attiny1614/sigrow.asm
M attiny1614/slpctrl.asm
M attiny1614/spi0.asm
M attiny1614/syscfg.asm
M attiny1614/tcb0.asm
M attiny1614/tcb1.asm
M attiny1614/tcd0.asm
M attiny1614/twi0.asm
M attiny1614/usart0.asm
M attiny1614/userrow.asm
M attiny1614/vporta.asm
M attiny1614/vportb.asm
M attiny1614/vportc.asm
M attiny1614/vref.asm
M attiny1614/wdt.asm
M attiny167/ac.asm
M attiny167/adc.asm
M attiny167/boot_load.asm
M attiny167/cpu.asm
M attiny167/current_source.asm
M attiny167/device.asm
M attiny167/eeprom.asm
M attiny167/exint.asm
M attiny167/fuse.asm
M attiny167/linuart.asm
M attiny167/lockbit.asm
M attiny167/porta.asm
M attiny167/portb.asm
M attiny167/spi.asm
M attiny167/tc0.asm
M attiny167/tc1.asm
M attiny167/usi.asm
M attiny167/wdt.asm
M attiny202/ac0.asm
M attiny202/adc0.asm
M attiny202/bod.asm
M attiny202/ccl.asm
M attiny202/clkctrl.asm
M attiny202/cpu.asm
M attiny202/cpuint.asm
M attiny202/crcscan.asm
M attiny202/device.asm
M attiny202/evsys.asm
M attiny202/fuse.asm
M attiny202/gpio.asm
M attiny202/lockbit.asm
M attiny202/nvmctrl.asm
M attiny202/porta.asm
M attiny202/portmux.asm
M attiny202/rstctrl.asm
M attiny202/rtc.asm
M attiny202/sigrow.asm
M attiny202/slpctrl.asm
M attiny202/spi0.asm
M attiny202/syscfg.asm
M attiny202/tcb0.asm
M attiny202/twi0.asm
M attiny202/usart0.asm
M attiny202/userrow.asm
M attiny202/vporta.asm
M attiny202/vportb.asm
M attiny202/vportc.asm
M attiny202/vref.asm
M attiny202/wdt.asm
M attiny2313/ac.asm
M attiny2313/cpu.asm
M attiny2313/device.asm
M attiny2313/eeprom.asm
M attiny2313/exint.asm
M attiny2313/fuse.asm
M attiny2313/lockbit.asm
M attiny2313/porta.asm
M attiny2313/portb.asm
M attiny2313/portd.asm
M attiny2313/tc0.asm
M attiny2313/tc1.asm
M attiny2313/usart.asm
M attiny2313/usi.asm
M attiny2313/wdt.asm
M attiny2313a/ac.asm
M attiny2313a/cpu.asm
M attiny2313a/device.asm
M attiny2313a/eeprom.asm
M attiny2313a/exint.asm
M attiny2313a/fuse.asm
M attiny2313a/lockbit.asm
M attiny2313a/porta.asm
M attiny2313a/portb.asm
M attiny2313a/portd.asm
M attiny2313a/tc0.asm
M attiny2313a/tc1.asm
M attiny2313a/usart.asm
M attiny2313a/usi.asm
M attiny2313a/wdt.asm
M attiny816/ac0.asm
M attiny816/adc0.asm
M attiny816/bod.asm
M attiny816/ccl.asm
M attiny816/clkctrl.asm
M attiny816/cpu.asm
M attiny816/cpuint.asm
M attiny816/crcscan.asm
M attiny816/dac0.asm
M attiny816/device.asm
M attiny816/evsys.asm
M attiny816/fuse.asm
M attiny816/gpio.asm
M attiny816/lockbit.asm
M attiny816/nvmctrl.asm
M attiny816/porta.asm
M attiny816/portb.asm
M attiny816/portc.asm
M attiny816/portmux.asm
M attiny816/rstctrl.asm
M attiny816/rtc.asm
M attiny816/sigrow.asm
M attiny816/slpctrl.asm
M attiny816/spi0.asm
M attiny816/syscfg.asm
M attiny816/tcb0.asm
M attiny816/tcd0.asm
M attiny816/twi0.asm
M attiny816/usart0.asm
M attiny816/userrow.asm
M attiny816/vporta.asm
M attiny816/vportb.asm
M attiny816/vportc.asm
M attiny816/vref.asm
M attiny816/wdt.asm
M attiny84/ac.asm
M attiny84/adc.asm
M attiny84/boot_load.asm
M attiny84/cpu.asm
M attiny84/device.asm
M attiny84/eeprom.asm
M attiny84/exint.asm
M attiny84/fuse.asm
M attiny84/lockbit.asm
M attiny84/porta.asm
M attiny84/portb.asm
M attiny84/tc0.asm
M attiny84/tc1.asm
M attiny84/usi.asm
M attiny84/wdt.asm
M attiny841/ac.asm
M attiny841/adc.asm
M attiny841/cpu.asm
M attiny841/device.asm
M attiny841/eeprom.asm
M attiny841/exint.asm
M attiny841/fuse.asm
M attiny841/lockbit.asm
M attiny841/porta.asm
M attiny841/portb.asm
M attiny841/spi.asm
M attiny841/tc0.asm
M attiny841/tc1.asm
M attiny841/tc2.asm
M attiny841/tocpm.asm
M attiny841/twi.asm
M attiny841/usart0.asm
M attiny841/usart1.asm
M attiny841/wdt.asm
M attiny85/ac.asm
M attiny85/adc.asm
M attiny85/boot_load.asm
M attiny85/cpu.asm
M attiny85/device.asm
M attiny85/eeprom.asm
M attiny85/exint.asm
M attiny85/fuse.asm
M attiny85/lockbit.asm
M attiny85/portb.asm
M attiny85/tc0.asm
M attiny85/tc1.asm
M attiny85/usi.asm
M attiny85/wdt.asm
M attiny861/ac.asm
M attiny861/adc.asm
M attiny861/boot_load.asm
M attiny861/cpu.asm
M attiny861/device.asm
M attiny861/eeprom.asm
M attiny861/exint.asm
M attiny861/fuse.asm
M attiny861/lockbit.asm
M attiny861/porta.asm
M attiny861/portb.asm
M attiny861/tc0.asm
M attiny861/tc1.asm
M attiny861/usi.asm
M attiny861/wdt.asm
M attiny88/ac.asm
M attiny88/adc.asm
M attiny88/cpu.asm
M attiny88/device.asm
M attiny88/eeprom.asm
M attiny88/exint.asm
M attiny88/fuse.asm
M attiny88/lockbit.asm
M attiny88/porta.asm
M attiny88/portb.asm
M attiny88/portc.asm
M attiny88/portd.asm
M attiny88/spi.asm
M attiny88/tc0.asm
M attiny88/tc1.asm
M attiny88/twi.asm
M attiny88/wdt.asm
M at90usb1286/ac.asm => at90usb1286/ac.asm +4 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; AC peripheral register map assembly header for AT90USB1286
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    ACSR
; Description: Analog Comparator Control And Status Register

.equ           ACSR       = 0x50
; Field:       ACIS
; Description: Analog Comparator Interrupt Mode Select


@@ 52,6 53,7 @@

; Register:    ADCSRB
; Description: ADC Control and Status Register B

.equ           ADCSRB       = 0x7B
; Field:       ACME
; Description: Analog Comparator Multiplexer Enable


@@ 61,6 63,7 @@

; Register:    DIDR1
; Description: No Description.

.equ           DIDR1       = 0x7F
; Field:       AIN0D
; Description: AIN0 Digital Input Disable

M at90usb1286/adc.asm => at90usb1286/adc.asm +6 -1
@@ 2,16 2,18 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; ADC peripheral register map assembly header for AT90USB1286
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    ADC
; Description: ADC Data Register  Bytes

.equ           ADC       = 0x78

; Register:    ADCSRA
; Description: The ADC Control and Status register

.equ           ADCSRA       = 0x7A
; Field:       ADPS
; Description: ADC Prescaler Select Bits


@@ 55,6 57,7 @@

; Register:    ADCSRB
; Description: ADC Control and Status Register B

.equ           ADCSRB       = 0x7B
; Field:       ADTS
; Description: ADC Auto Trigger Sources


@@ 79,6 82,7 @@

; Register:    ADMUX
; Description: The ADC multiplexer Selection Register

.equ           ADMUX       = 0x7C
; Field:       MUX
; Description: Analog Channel and Gain Selection Bits


@@ 104,6 108,7 @@

; Register:    DIDR0
; Description: Digital Input Disable Register 1

.equ           DIDR0       = 0x7E
; Field:       ADC0D
; Description: ADC0 Digital input Disable

M at90usb1286/boot_load.asm => at90usb1286/boot_load.asm +2 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; BOOT_LOAD peripheral register map assembly header for AT90USB1286
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    SPMCSR
; Description: Store Program Memory Control Register

.equ           SPMCSR       = 0x57
; Field:       SPMEN
; Description: Store Program Memory Enable

M at90usb1286/cpu.asm => at90usb1286/cpu.asm +15 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; CPU peripheral register map assembly header for AT90USB1286
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    CLKPR
; Description: No Description.

.equ           CLKPR       = 0x61
; Field:       CLKPS
; Description: No Description.


@@ 33,10 34,12 @@

; Register:    EIND
; Description: Extended Indirect Register

.equ           EIND       = 0x5C

; Register:    GPIOR0
; Description: General Purpose IO Register 0

.equ           GPIOR0       = 0x3E
; Field:       GPIOR00
; Description: General Purpose IO Register 0 bit 0


@@ 81,6 84,7 @@

; Register:    GPIOR1
; Description: General Purpose IO Register 1

.equ           GPIOR1       = 0x4A
; Field:       GPIOR
; Description: General Purpose IO Register 1 bis


@@ 91,6 95,7 @@

; Register:    GPIOR2
; Description: General Purpose IO Register 2

.equ           GPIOR2       = 0x4B
; Field:       GPIOR
; Description: General Purpose IO Register 2 bis


@@ 101,6 106,7 @@

; Register:    MCUCR
; Description: MCU Control Register

.equ           MCUCR       = 0x55
; Field:       IVCE
; Description: Interrupt Vector Change Enable


@@ 125,6 131,7 @@

; Register:    MCUSR
; Description: MCU Status Register

.equ           MCUSR       = 0x54
; Field:       PORF
; Description: Power-on reset flag


@@ 154,6 161,7 @@

; Register:    OSCCAL
; Description: Oscillator Calibration Value

.equ           OSCCAL       = 0x66
; Field:       OSCCAL
; Description: Oscillator Calibration 


@@ 164,6 172,7 @@

; Register:    PRR0
; Description: Power Reduction Register0

.equ           PRR0       = 0x64
; Field:       PRADC
; Description: Power Reduction ADC


@@ 198,6 207,7 @@

; Register:    PRR1
; Description: Power Reduction Register1

.equ           PRR1       = 0x65
; Field:       PRUSART1
; Description: Power Reduction USART1


@@ 217,10 227,12 @@

; Register:    RAMPZ
; Description: RAM Page Z Select Register

.equ           RAMPZ       = 0x5B

; Register:    SMCR
; Description: Sleep Mode Control Register

.equ           SMCR       = 0x53
; Field:       SE
; Description: Sleep Enable


@@ 245,6 257,7 @@

; Register:    XMCRA
; Description: External Memory Control Register A

.equ           XMCRA       = 0x74
; Field:       SRW0
; Description: Wait state select bit lower page


@@ 291,6 304,7 @@

; Register:    XMCRB
; Description: External Memory Control Register B

.equ           XMCRB       = 0x75
; Field:       XMM
; Description: External Memory High Mask

M at90usb1286/device.asm => at90usb1286/device.asm +1 -1
@@ 2,7 2,7 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; Device definition assembly header for AT90USB1286
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; DEVICE SPECIFICATIONS
.device AT90USB1286

M at90usb1286/eeprom.asm => at90usb1286/eeprom.asm +4 -1
@@ 2,16 2,18 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; EEPROM peripheral register map assembly header for AT90USB1286
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    EEAR
; Description: EEPROM Address Register Low Bytes

.equ           EEAR       = 0x41

; Register:    EECR
; Description: EEPROM Control Register

.equ           EECR       = 0x3F
; Field:       EERE
; Description: EEPROM Read Enable


@@ 46,4 48,5 @@

; Register:    EEDR
; Description: EEPROM Data Register

.equ           EEDR       = 0x40

M at90usb1286/exint.asm => at90usb1286/exint.asm +8 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; EXINT peripheral register map assembly header for AT90USB1286
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    EICRA
; Description: External Interrupt Control Register A

.equ           EICRA       = 0x69
; Field:       ISC0
; Description: External Interrupt Sense Control Bit


@@ 56,6 57,7 @@

; Register:    EICRB
; Description: External Interrupt Control Register B

.equ           EICRB       = 0x6A
; Field:       ISC4
; Description: External Interrupt 7-4 Sense Control Bit


@@ 104,6 106,7 @@

; Register:    EIFR
; Description: External Interrupt Flag Register

.equ           EIFR       = 0x3C
; Field:       INTF
; Description: External Interrupt Flags


@@ 114,6 117,7 @@

; Register:    EIMSK
; Description: External Interrupt Mask Register

.equ           EIMSK       = 0x3D
; Field:       INT
; Description: External Interrupt Request 7 Enable


@@ 124,6 128,7 @@

; Register:    PCICR
; Description: Pin Change Interrupt Control Register

.equ           PCICR       = 0x68
; Field:       PCIE0
; Description: Pin Change Interrupt Enable 0


@@ 133,6 138,7 @@

; Register:    PCIFR
; Description: Pin Change Interrupt Flag Register

.equ           PCIFR       = 0x3B
; Field:       PCIF0
; Description: Pin Change Interrupt Flag 0


@@ 142,4 148,5 @@

; Register:    PCMSK0
; Description: Pin Change Mask Register 0

.equ           PCMSK0       = 0x6B

M at90usb1286/fuse.asm => at90usb1286/fuse.asm +4 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; FUSE peripheral register map assembly header for AT90USB1286
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    EXTENDED
; Description: No Description.

.equ           EXTENDED       = 0x02
; Field:       BODLEVEL
; Description: Brown-out Detector trigger level


@@ 32,6 33,7 @@

; Register:    HIGH
; Description: No Description.

.equ           HIGH       = 0x01
; Field:       BOOTRST
; Description: Boot Reset vector Enabled


@@ 77,6 79,7 @@

; Register:    LOW
; Description: No Description.

.equ           LOW       = 0x00
; Field:       SUT_CKSEL
; Description: Select Clock Source

M at90usb1286/jtag.asm => at90usb1286/jtag.asm +4 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; JTAG peripheral register map assembly header for AT90USB1286
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    MCUCR
; Description: MCU Control Register

.equ           MCUCR       = 0x55
; Field:       JTD
; Description: JTAG Interface Disable


@@ 17,6 18,7 @@

; Register:    MCUSR
; Description: MCU Status Register

.equ           MCUSR       = 0x54
; Field:       JTRF
; Description: JTAG Reset Flag


@@ 26,4 28,5 @@

; Register:    OCDR
; Description: On-Chip Debug Related Register in I/O Memory

.equ           OCDR       = 0x51

M at90usb1286/lockbit.asm => at90usb1286/lockbit.asm +2 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; LOCKBIT peripheral register map assembly header for AT90USB1286
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    LOCKBIT
; Description: No Description.

.equ           LOCKBIT       = 0x00
; Field:       LB
; Description: Memory Lock

M at90usb1286/pll.asm => at90usb1286/pll.asm +2 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; PLL peripheral register map assembly header for AT90USB1286
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    PLLCSR
; Description: PLL Status and Control register

.equ           PLLCSR       = 0x49
; Field:       PLOCK
; Description: PLL Lock Status Bit

M at90usb1286/porta.asm => at90usb1286/porta.asm +4 -1
@@ 2,18 2,21 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; PORTA peripheral register map assembly header for AT90USB1286
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    DDRA
; Description: Port A Data Direction Register

.equ           DDRA       = 0x21

; Register:    PINA
; Description: Port A Input Pins

.equ           PINA       = 0x20

; Register:    PORTA
; Description: Port A Data Register

.equ           PORTA       = 0x22

M at90usb1286/portb.asm => at90usb1286/portb.asm +4 -1
@@ 2,18 2,21 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; PORTB peripheral register map assembly header for AT90USB1286
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    DDRB
; Description: Port B Data Direction Register

.equ           DDRB       = 0x24

; Register:    PINB
; Description: Port B Input Pins

.equ           PINB       = 0x23

; Register:    PORTB
; Description: Port B Data Register

.equ           PORTB       = 0x25

M at90usb1286/portc.asm => at90usb1286/portc.asm +4 -1
@@ 2,18 2,21 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; PORTC peripheral register map assembly header for AT90USB1286
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    DDRC
; Description: Port C Data Direction Register

.equ           DDRC       = 0x27

; Register:    PINC
; Description: Port C Input Pins

.equ           PINC       = 0x26

; Register:    PORTC
; Description: Port C Data Register

.equ           PORTC       = 0x28

M at90usb1286/portd.asm => at90usb1286/portd.asm +4 -1
@@ 2,18 2,21 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; PORTD peripheral register map assembly header for AT90USB1286
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    DDRD
; Description: Port D Data Direction Register

.equ           DDRD       = 0x2A

; Register:    PIND
; Description: Port D Input Pins

.equ           PIND       = 0x29

; Register:    PORTD
; Description: Port D Data Register

.equ           PORTD       = 0x2B

M at90usb1286/porte.asm => at90usb1286/porte.asm +4 -1
@@ 2,18 2,21 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; PORTE peripheral register map assembly header for AT90USB1286
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    DDRE
; Description: Data Direction Register, Port E

.equ           DDRE       = 0x2D

; Register:    PINE
; Description: Input Pins, Port E

.equ           PINE       = 0x2C

; Register:    PORTE
; Description: Data Register, Port E

.equ           PORTE       = 0x2E

M at90usb1286/portf.asm => at90usb1286/portf.asm +4 -1
@@ 2,18 2,21 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; PORTF peripheral register map assembly header for AT90USB1286
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    DDRF
; Description: Data Direction Register, Port F

.equ           DDRF       = 0x30

; Register:    PINF
; Description: Input Pins, Port F

.equ           PINF       = 0x2F

; Register:    PORTF
; Description: Data Register, Port F

.equ           PORTF       = 0x31

M at90usb1286/spi.asm => at90usb1286/spi.asm +4 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; SPI peripheral register map assembly header for AT90USB1286
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    SPCR
; Description: SPI Control Register

.equ           SPCR       = 0x4C
; Field:       SPR
; Description: SPI Clock Rate Selects


@@ 53,10 54,12 @@

; Register:    SPDR
; Description: SPI Data Register

.equ           SPDR       = 0x4E

; Register:    SPSR
; Description: SPI Status Register

.equ           SPSR       = 0x4D
; Field:       SPI2X
; Description: Double SPI Speed Bit

M at90usb1286/tc0.asm => at90usb1286/tc0.asm +9 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; TC0 peripheral register map assembly header for AT90USB1286
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    GTCCR
; Description: General Timer/Counter Control Register

.equ           GTCCR       = 0x43
; Field:       PSRSYNC
; Description: Prescaler Reset Timer/Counter1 and Timer/Counter0


@@ 22,14 23,17 @@

; Register:    OCR0A
; Description: Timer/Counter0 Output Compare Register

.equ           OCR0A       = 0x47

; Register:    OCR0B
; Description: Timer/Counter0 Output Compare Register

.equ           OCR0B       = 0x48

; Register:    TCCR0A
; Description: Timer/Counter  Control Register A

.equ           TCCR0A       = 0x44
; Field:       WGM0
; Description: Waveform Generation Mode


@@ 52,6 56,7 @@

; Register:    TCCR0B
; Description: Timer/Counter Control Register B

.equ           TCCR0B       = 0x45
; Field:       CS0
; Description: Clock Select


@@ 86,10 91,12 @@

; Register:    TCNT0
; Description: Timer/Counter0

.equ           TCNT0       = 0x46

; Register:    TIFR0
; Description: Timer/Counter0 Interrupt Flag register

.equ           TIFR0       = 0x35
; Field:       TOV0
; Description: Timer/Counter0 Overflow Flag


@@ 109,6 116,7 @@

; Register:    TIMSK0
; Description: Timer/Counter0 Interrupt Mask Register

.equ           TIMSK0       = 0x6E
; Field:       TOIE0
; Description: Timer/Counter0 Overflow Interrupt Enable

M at90usb1286/tc1.asm => at90usb1286/tc1.asm +11 -1
@@ 2,28 2,33 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; TC1 peripheral register map assembly header for AT90USB1286
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    ICR1
; Description: Timer/Counter1 Input Capture Register  Bytes

.equ           ICR1       = 0x86

; Register:    OCR1A
; Description: Timer/Counter1 Output Compare Register A  Bytes

.equ           OCR1A       = 0x88

; Register:    OCR1B
; Description: Timer/Counter1 Output Compare Register B  Bytes

.equ           OCR1B       = 0x8A

; Register:    OCR1C
; Description: Timer/Counter1 Output Compare Register C  Bytes

.equ           OCR1C       = 0x8C

; Register:    TCCR1A
; Description: Timer/Counter1 Control Register A

.equ           TCCR1A       = 0x80
; Field:       WGM1
; Description: Waveform Generation Mode


@@ 52,6 57,7 @@

; Register:    TCCR1B
; Description: Timer/Counter1 Control Register B

.equ           TCCR1B       = 0x81
; Field:       CS1
; Description: Prescaler source of Timer/Counter 1


@@ 87,6 93,7 @@

; Register:    TCCR1C
; Description: Timer/Counter 1 Control Register C

.equ           TCCR1C       = 0x82
; Field:       FOC1C
; Description: Force Output Compare 1C


@@ 106,10 113,12 @@

; Register:    TCNT1
; Description: Timer/Counter1  Bytes

.equ           TCNT1       = 0x84

; Register:    TIFR1
; Description: Timer/Counter1 Interrupt Flag register

.equ           TIFR1       = 0x36
; Field:       TOV1
; Description: Timer/Counter1 Overflow Flag


@@ 139,6 148,7 @@

; Register:    TIMSK1
; Description: Timer/Counter1 Interrupt Mask Register

.equ           TIMSK1       = 0x6F
; Field:       TOIE1
; Description: Timer/Counter1 Overflow Interrupt Enable

M at90usb1286/tc2.asm => at90usb1286/tc2.asm +10 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; TC2 peripheral register map assembly header for AT90USB1286
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    ASSR
; Description: Asynchronous Status Register

.equ           ASSR       = 0xB6
; Field:       TCR2BUB
; Description: Timer/Counter Control Register2 Update Busy


@@ 47,6 48,7 @@

; Register:    GTCCR
; Description: General Timer Counter Control register

.equ           GTCCR       = 0x43
; Field:       PSRASY
; Description: Prescaler Reset Timer/Counter2


@@ 61,14 63,17 @@

; Register:    OCR2A
; Description: Timer/Counter2 Output Compare Register A

.equ           OCR2A       = 0xB3

; Register:    OCR2B
; Description: Timer/Counter2 Output Compare Register B

.equ           OCR2B       = 0xB4

; Register:    TCCR2A
; Description: Timer/Counter2 Control Register A

.equ           TCCR2A       = 0xB0
; Field:       WGM2
; Description: Waveform Genration Mode


@@ 91,6 96,7 @@

; Register:    TCCR2B
; Description: Timer/Counter2 Control Register B

.equ           TCCR2B       = 0xB1
; Field:       CS2
; Description: Clock Select bits


@@ 125,10 131,12 @@

; Register:    TCNT2
; Description: Timer/Counter2

.equ           TCNT2       = 0xB2

; Register:    TIFR2
; Description: Timer/Counter Interrupt Flag Register

.equ           TIFR2       = 0x37
; Field:       TOV2
; Description: Timer/Counter2 Overflow Flag


@@ 148,6 156,7 @@

; Register:    TIMSK2
; Description: Timer/Counter Interrupt Mask register

.equ           TIMSK2       = 0x70
; Field:       TOIE2
; Description: Timer/Counter2 Overflow Interrupt Enable

M at90usb1286/tc3.asm => at90usb1286/tc3.asm +11 -1
@@ 2,28 2,33 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; TC3 peripheral register map assembly header for AT90USB1286
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    ICR3
; Description: Timer/Counter3 Input Capture Register  Bytes

.equ           ICR3       = 0x96

; Register:    OCR3A
; Description: Timer/Counter3 Output Compare Register A  Bytes

.equ           OCR3A       = 0x98

; Register:    OCR3B
; Description: Timer/Counter3 Output Compare Register B  Bytes

.equ           OCR3B       = 0x9A

; Register:    OCR3C
; Description: Timer/Counter3 Output Compare Register B  Bytes

.equ           OCR3C       = 0x9C

; Register:    TCCR3A
; Description: Timer/Counter3 Control Register A

.equ           TCCR3A       = 0x90
; Field:       WGM3
; Description: Waveform Generation Mode


@@ 52,6 57,7 @@

; Register:    TCCR3B
; Description: Timer/Counter3 Control Register B

.equ           TCCR3B       = 0x91
; Field:       CS3
; Description: Prescaler source of Timer/Counter 3


@@ 87,6 93,7 @@

; Register:    TCCR3C
; Description: Timer/Counter 3 Control Register C

.equ           TCCR3C       = 0x92
; Field:       FOC3C
; Description: Force Output Compare 3C


@@ 106,10 113,12 @@

; Register:    TCNT3
; Description: Timer/Counter3  Bytes

.equ           TCNT3       = 0x94

; Register:    TIFR3
; Description: Timer/Counter3 Interrupt Flag register

.equ           TIFR3       = 0x38
; Field:       TOV3
; Description: Timer/Counter3 Overflow Flag


@@ 139,6 148,7 @@

; Register:    TIMSK3
; Description: Timer/Counter3 Interrupt Mask Register

.equ           TIMSK3       = 0x71
; Field:       TOIE3
; Description: Timer/Counter3 Overflow Interrupt Enable

M at90usb1286/twi.asm => at90usb1286/twi.asm +7 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; TWI peripheral register map assembly header for AT90USB1286
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    TWAMR
; Description: TWI (Slave) Address Mask Register

.equ           TWAMR       = 0xBD
; Field:       TWAM
; Description: TWI (Slave) Address Mask Bits


@@ 18,6 19,7 @@

; Register:    TWAR
; Description: TWI (Slave) Address register

.equ           TWAR       = 0xBA
; Field:       TWGCE
; Description: TWI General Call Recognition Enable Bit


@@ 33,10 35,12 @@

; Register:    TWBR
; Description: TWI Bit Rate register

.equ           TWBR       = 0xB8

; Register:    TWCR
; Description: TWI Control Register

.equ           TWCR       = 0xBC
; Field:       TWIE
; Description: TWI Interrupt Enable


@@ 76,10 80,12 @@

; Register:    TWDR
; Description: TWI Data register

.equ           TWDR       = 0xBB

; Register:    TWSR
; Description: TWI Status Register

.equ           TWSR       = 0xB9
; Field:       TWPS
; Description: TWI Prescaler

M at90usb1286/usart1.asm => at90usb1286/usart1.asm +6 -1
@@ 2,16 2,18 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; USART1 peripheral register map assembly header for AT90USB1286
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    UBRR1
; Description: USART Baud Rate Register  Bytes

.equ           UBRR1       = 0xCC

; Register:    UCSR1A
; Description: USART Control and Status Register A

.equ           UCSR1A       = 0xC8
; Field:       MPCM1
; Description: Multi-processor Communication Mode


@@ 56,6 58,7 @@

; Register:    UCSR1B
; Description: USART Control and Status Register B

.equ           UCSR1B       = 0xC9
; Field:       TXB81
; Description: Transmit Data Bit 8


@@ 100,6 103,7 @@

; Register:    UCSR1C
; Description: USART Control and Status Register C

.equ           UCSR1C       = 0xCA
; Field:       UCPOL1
; Description: Clock Polarity


@@ 145,4 149,5 @@

; Register:    UDR1
; Description: USART I/O Data Register

.equ           UDR1       = 0xCE

M at90usb1286/usb_device.asm => at90usb1286/usb_device.asm +20 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; USB_DEVICE peripheral register map assembly header for AT90USB1286
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    UDADDR
; Description: No Description.

.equ           UDADDR       = 0xE3
; Field:       UADD
; Description: No Description.


@@ 23,6 24,7 @@

; Register:    UDCON
; Description: No Description.

.equ           UDCON       = 0xE0
; Field:       DETACH
; Description: No Description.


@@ 42,10 44,12 @@

; Register:    UDFNUM
; Description: No Description.

.equ           UDFNUM       = 0xE4

; Register:    UDIEN
; Description: No Description.

.equ           UDIEN       = 0xE2
; Field:       SUSPE
; Description: No Description.


@@ 80,6 84,7 @@

; Register:    UDINT
; Description: No Description.

.equ           UDINT       = 0xE1
; Field:       SUSPI
; Description: No Description.


@@ 114,6 119,7 @@

; Register:    UDMFN
; Description: No Description.

.equ           UDMFN       = 0xE6
; Field:       FNCERR
; Description: No Description.


@@ 123,14 129,17 @@

; Register:    UEBCHX
; Description: No Description.

.equ           UEBCHX       = 0xF3

; Register:    UEBCLX
; Description: No Description.

.equ           UEBCLX       = 0xF2

; Register:    UECFG0X
; Description: No Description.

.equ           UECFG0X       = 0xEC
; Field:       EPDIR
; Description: No Description.


@@ 146,6 155,7 @@

; Register:    UECFG1X
; Description: No Description.

.equ           UECFG1X       = 0xED
; Field:       ALLOC
; Description: No Description.


@@ 167,6 177,7 @@

; Register:    UECONX
; Description: No Description.

.equ           UECONX       = 0xEB
; Field:       EPEN
; Description: No Description.


@@ 191,10 202,12 @@

; Register:    UEDATX
; Description: No Description.

.equ           UEDATX       = 0xF1

; Register:    UEIENX
; Description: No Description.

.equ           UEIENX       = 0xF0
; Field:       TXINE
; Description: No Description.


@@ 234,10 247,12 @@

; Register:    UEINT
; Description: No Description.

.equ           UEINT       = 0xF4

; Register:    UEINTX
; Description: No Description.

.equ           UEINTX       = 0xE8
; Field:       TXINI
; Description: No Description.


@@ 282,10 297,12 @@

; Register:    UENUM
; Description: No Description.

.equ           UENUM       = 0xE9

; Register:    UERST
; Description: No Description.

.equ           UERST       = 0xEA
; Field:       EPRST
; Description: No Description.


@@ 296,6 313,7 @@

; Register:    UESTA0X
; Description: No Description.

.equ           UESTA0X       = 0xEE
; Field:       NBUSYBK
; Description: No Description.


@@ 327,6 345,7 @@

; Register:    UESTA1X
; Description: No Description.

.equ           UESTA1X       = 0xEF
; Field:       CURRBK
; Description: No Description.

M at90usb1286/usb_global.asm => at90usb1286/usb_global.asm +5 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; USB_GLOBAL peripheral register map assembly header for AT90USB1286
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    UHWCON
; Description: USB Hardware Configuration Register

.equ           UHWCON       = 0xD7
; Field:       UVREGE
; Description: No Description.


@@ 32,6 33,7 @@

; Register:    USBCON
; Description: USB General Control Register

.equ           USBCON       = 0xD8
; Field:       VBUSTE
; Description: No Description.


@@ 66,6 68,7 @@

; Register:    USBINT
; Description: No Description.

.equ           USBINT       = 0xDA
; Field:       VBUSTI
; Description: No Description.


@@ 80,6 83,7 @@

; Register:    USBSTA
; Description: No Description.

.equ           USBSTA       = 0xD9
; Field:       VBUS
; Description: No Description.

M at90usb1286/wdt.asm => at90usb1286/wdt.asm +2 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; WDT peripheral register map assembly header for AT90USB1286
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    WDTCSR
; Description: Watchdog Timer Control Register

.equ           WDTCSR       = 0x60
; Field:       WDP
; Description: Watchdog Timer Prescaler Bits

M atmega1280/ac.asm => atmega1280/ac.asm +4 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; AC peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    ACSR
; Description: Analog Comparator Control And Status Register

.equ           ACSR       = 0x50
; Field:       ACIS
; Description: Analog Comparator Interrupt Mode Select


@@ 52,6 53,7 @@

; Register:    ADCSRB
; Description: ADC Control and Status Register B

.equ           ADCSRB       = 0x7B
; Field:       ACME
; Description: Analog Comparator Multiplexer Enable


@@ 61,6 63,7 @@

; Register:    DIDR1
; Description: Digital Input Disable Register 1

.equ           DIDR1       = 0x7F
; Field:       AIN0D
; Description: AIN0 Digital Input Disable

M atmega1280/adc.asm => atmega1280/adc.asm +7 -1
@@ 2,16 2,18 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; ADC peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    ADC
; Description: ADC Data Register  Bytes

.equ           ADC       = 0x78

; Register:    ADCSRA
; Description: The ADC Control and Status register A

.equ           ADCSRA       = 0x7A
; Field:       ADPS
; Description: ADC  Prescaler Select Bits


@@ 55,6 57,7 @@

; Register:    ADCSRB
; Description: The ADC Control and Status register B

.equ           ADCSRB       = 0x7B
; Field:       ADTS
; Description: ADC Auto Trigger Source bits


@@ 84,6 87,7 @@

; Register:    ADMUX
; Description: The ADC multiplexer Selection Register

.equ           ADMUX       = 0x7C
; Field:       MUX
; Description: Analog Channel and Gain Selection Bits


@@ 109,6 113,7 @@

; Register:    DIDR0
; Description: Digital Input Disable Register

.equ           DIDR0       = 0x7E
; Field:       ADC0D
; Description: No Description.


@@ 153,6 158,7 @@

; Register:    DIDR2
; Description: Digital Input Disable Register

.equ           DIDR2       = 0x7D
; Field:       ADC8D
; Description: No Description.

M atmega1280/boot_load.asm => atmega1280/boot_load.asm +2 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; BOOT_LOAD peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    SPMCSR
; Description: Store Program Memory Control Register

.equ           SPMCSR       = 0x57
; Field:       SPMEN
; Description: Store Program Memory Enable

M atmega1280/cpu.asm => atmega1280/cpu.asm +15 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; CPU peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    CLKPR
; Description: No Description.

.equ           CLKPR       = 0x61
; Field:       CLKPS
; Description: No Description.


@@ 33,10 34,12 @@

; Register:    EIND
; Description: Extended Indirect Register

.equ           EIND       = 0x5C

; Register:    GPIOR0
; Description: General Purpose IO Register 0

.equ           GPIOR0       = 0x3E
; Field:       GPIOR00
; Description: General Purpose IO Register 0 bit 0


@@ 81,6 84,7 @@

; Register:    GPIOR1
; Description: General Purpose IO Register 1

.equ           GPIOR1       = 0x4A
; Field:       GPIOR
; Description: General Purpose IO Register 1 bis


@@ 91,6 95,7 @@

; Register:    GPIOR2
; Description: General Purpose IO Register 2

.equ           GPIOR2       = 0x4B
; Field:       GPIOR
; Description: General Purpose IO Register 2 bis


@@ 101,6 106,7 @@

; Register:    MCUCR
; Description: MCU Control Register

.equ           MCUCR       = 0x55
; Field:       IVCE
; Description: Interrupt Vector Change Enable


@@ 125,6 131,7 @@

; Register:    MCUSR
; Description: MCU Status Register

.equ           MCUSR       = 0x54
; Field:       PORF
; Description: Power-on reset flag


@@ 154,6 161,7 @@

; Register:    OSCCAL
; Description: Oscillator Calibration Value

.equ           OSCCAL       = 0x66
; Field:       OSCCAL
; Description: Oscillator Calibration 


@@ 164,6 172,7 @@

; Register:    PRR0
; Description: Power Reduction Register0

.equ           PRR0       = 0x64
; Field:       PRADC
; Description: Power Reduction ADC


@@ 203,6 212,7 @@

; Register:    PRR1
; Description: Power Reduction Register1

.equ           PRR1       = 0x65
; Field:       PRUSART1
; Description: Power Reduction USART1


@@ 237,10 247,12 @@

; Register:    RAMPZ
; Description: RAM Page Z Select Register

.equ           RAMPZ       = 0x5B

; Register:    SMCR
; Description: Sleep Mode Control Register

.equ           SMCR       = 0x53
; Field:       SE
; Description: Sleep Enable


@@ 265,6 277,7 @@

; Register:    XMCRA
; Description: External Memory Control Register A

.equ           XMCRA       = 0x74
; Field:       SRW0
; Description: Wait state select bit lower page


@@ 311,6 324,7 @@

; Register:    XMCRB
; Description: External Memory Control Register B

.equ           XMCRB       = 0x75
; Field:       XMM
; Description: External Memory High Mask

M atmega1280/device.asm => atmega1280/device.asm +1 -1
@@ 2,7 2,7 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; Device definition assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; DEVICE SPECIFICATIONS
.device ATmega1280

M atmega1280/eeprom.asm => atmega1280/eeprom.asm +4 -1
@@ 2,16 2,18 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; EEPROM peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    EEAR
; Description: EEPROM Address Register Low Bytes

.equ           EEAR       = 0x41

; Register:    EECR
; Description: EEPROM Control Register

.equ           EECR       = 0x3F
; Field:       EERE
; Description: EEPROM Read Enable


@@ 46,4 48,5 @@

; Register:    EEDR
; Description: EEPROM Data Register

.equ           EEDR       = 0x40

M atmega1280/exint.asm => atmega1280/exint.asm +10 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; EXINT peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    EICRA
; Description: External Interrupt Control Register A

.equ           EICRA       = 0x69
; Field:       ISC0
; Description: External Interrupt Sense Control Bit


@@ 56,6 57,7 @@

; Register:    EICRB
; Description: External Interrupt Control Register B

.equ           EICRB       = 0x6A
; Field:       ISC4
; Description: External Interrupt 7-4 Sense Control Bit


@@ 104,6 106,7 @@

; Register:    EIFR
; Description: External Interrupt Flag Register

.equ           EIFR       = 0x3C
; Field:       INTF
; Description: External Interrupt Flags


@@ 114,6 117,7 @@

; Register:    EIMSK
; Description: External Interrupt Mask Register

.equ           EIMSK       = 0x3D
; Field:       INT
; Description: External Interrupt Request 7 Enable


@@ 124,6 128,7 @@

; Register:    PCICR
; Description: Pin Change Interrupt Control Register

.equ           PCICR       = 0x68
; Field:       PCIE
; Description: Pin Change Interrupt Enables


@@ 134,6 139,7 @@

; Register:    PCIFR
; Description: Pin Change Interrupt Flag Register

.equ           PCIFR       = 0x3B
; Field:       PCIF
; Description: Pin Change Interrupt Flags


@@ 144,6 150,7 @@

; Register:    PCMSK0
; Description: Pin Change Mask Register 0

.equ           PCMSK0       = 0x6B
; Field:       PCINT
; Description: Pin Change Enable bits


@@ 154,6 161,7 @@

; Register:    PCMSK1
; Description: Pin Change Mask Register 1

.equ           PCMSK1       = 0x6C
; Field:       PCINT
; Description: Pin Change Enable bits


@@ 164,6 172,7 @@

; Register:    PCMSK2
; Description: Pin Change Mask Register 2

.equ           PCMSK2       = 0x6D
; Field:       PCINT
; Description: Pin Change Enable bits

M atmega1280/fuse.asm => atmega1280/fuse.asm +4 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; FUSE peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    EXTENDED
; Description: No Description.

.equ           EXTENDED       = 0x02
; Field:       BODLEVEL
; Description: Brown-out Detector trigger level


@@ 23,6 24,7 @@

; Register:    HIGH
; Description: No Description.

.equ           HIGH       = 0x01
; Field:       BOOTRST
; Description: Boot Reset vector Enabled


@@ 68,6 70,7 @@

; Register:    LOW
; Description: No Description.

.equ           LOW       = 0x00
; Field:       SUT_CKSEL
; Description: Select Clock Source

M atmega1280/jtag.asm => atmega1280/jtag.asm +4 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; JTAG peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    MCUCR
; Description: MCU Control Register

.equ           MCUCR       = 0x55
; Field:       JTD
; Description: JTAG Interface Disable


@@ 17,6 18,7 @@

; Register:    MCUSR
; Description: MCU Status Register

.equ           MCUSR       = 0x54
; Field:       JTRF
; Description: JTAG Reset Flag


@@ 26,4 28,5 @@

; Register:    OCDR
; Description: On-Chip Debug Related Register in I/O Memory

.equ           OCDR       = 0x51

M atmega1280/lockbit.asm => atmega1280/lockbit.asm +2 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; LOCKBIT peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    LOCKBIT
; Description: No Description.

.equ           LOCKBIT       = 0x00
; Field:       LB
; Description: Memory Lock

M atmega1280/porta.asm => atmega1280/porta.asm +4 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; PORTA peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    DDRA
; Description: Port A Data Direction Register

.equ           DDRA       = 0x21
; Field:       PA0
; Description: Pin A0


@@ 52,6 53,7 @@

; Register:    PINA
; Description: Port A Input Pins

.equ           PINA       = 0x20
; Field:       PA0
; Description: Pin A0


@@ 96,6 98,7 @@

; Register:    PORTA
; Description: Port A Data Register

.equ           PORTA       = 0x22
; Field:       PA0
; Description: Pin A0

M atmega1280/portb.asm => atmega1280/portb.asm +4 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; PORTB peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    DDRB
; Description: Port B Data Direction Register

.equ           DDRB       = 0x24
; Field:       PB0
; Description: Pin B0


@@ 52,6 53,7 @@

; Register:    PINB
; Description: Port B Input Pins

.equ           PINB       = 0x23
; Field:       PB0
; Description: Pin B0


@@ 96,6 98,7 @@

; Register:    PORTB
; Description: Port B Data Register

.equ           PORTB       = 0x25
; Field:       PB0
; Description: Pin B0

M atmega1280/portc.asm => atmega1280/portc.asm +4 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; PORTC peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    DDRC
; Description: Port C Data Direction Register

.equ           DDRC       = 0x27
; Field:       PC0
; Description: Pin C0


@@ 52,6 53,7 @@

; Register:    PINC
; Description: Port C Input Pins

.equ           PINC       = 0x26
; Field:       PC0
; Description: Pin C0


@@ 96,6 98,7 @@

; Register:    PORTC
; Description: Port C Data Register

.equ           PORTC       = 0x28
; Field:       PC0
; Description: Pin C0

M atmega1280/portd.asm => atmega1280/portd.asm +4 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; PORTD peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    DDRD
; Description: Port D Data Direction Register

.equ           DDRD       = 0x2A
; Field:       PD0
; Description: Pin D0


@@ 52,6 53,7 @@

; Register:    PIND
; Description: Port D Input Pins

.equ           PIND       = 0x29
; Field:       PD0
; Description: Pin D0


@@ 96,6 98,7 @@

; Register:    PORTD
; Description: Port D Data Register

.equ           PORTD       = 0x2B
; Field:       PD0
; Description: Pin D0

M atmega1280/porte.asm => atmega1280/porte.asm +4 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; PORTE peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    DDRE
; Description: Data Direction Register, Port E

.equ           DDRE       = 0x2D
; Field:       PE0
; Description: Pin E0


@@ 52,6 53,7 @@

; Register:    PINE
; Description: Input Pins, Port E

.equ           PINE       = 0x2C
; Field:       PE0
; Description: Pin E0


@@ 96,6 98,7 @@

; Register:    PORTE
; Description: Data Register, Port E

.equ           PORTE       = 0x2E
; Field:       PE0
; Description: Pin E0

M atmega1280/portf.asm => atmega1280/portf.asm +4 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; PORTF peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    DDRF
; Description: Data Direction Register, Port F

.equ           DDRF       = 0x30
; Field:       PF0
; Description: Pin F0


@@ 52,6 53,7 @@

; Register:    PINF
; Description: Input Pins, Port F

.equ           PINF       = 0x2F
; Field:       PF0
; Description: Pin F0


@@ 96,6 98,7 @@

; Register:    PORTF
; Description: Data Register, Port F

.equ           PORTF       = 0x31
; Field:       PF0
; Description: Pin F0

M atmega1280/portg.asm => atmega1280/portg.asm +4 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; PORTG peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    DDRG
; Description: Data Direction Register, Port G

.equ           DDRG       = 0x33
; Field:       PG0
; Description: Pin G0


@@ 52,6 53,7 @@

; Register:    PING
; Description: Input Pins, Port G

.equ           PING       = 0x32
; Field:       PG0
; Description: Pin G0


@@ 96,6 98,7 @@

; Register:    PORTG
; Description: Data Register, Port G

.equ           PORTG       = 0x34
; Field:       PG0
; Description: Pin G0

M atmega1280/porth.asm => atmega1280/porth.asm +4 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; PORTH peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    DDRH
; Description: PORT H Data Direction Register

.equ           DDRH       = 0x101
; Field:       PH0
; Description: Pin H0


@@ 52,6 53,7 @@

; Register:    PINH
; Description: PORT H Input Pins

.equ           PINH       = 0x100
; Field:       PH0
; Description: Pin H0


@@ 96,6 98,7 @@

; Register:    PORTH
; Description: PORT H Data Register

.equ           PORTH       = 0x102
; Field:       PH0
; Description: Pin H0

M atmega1280/portj.asm => atmega1280/portj.asm +4 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; PORTJ peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    DDRJ
; Description: PORT J Data Direction Register

.equ           DDRJ       = 0x104
; Field:       PJ0
; Description: Pin J0


@@ 52,6 53,7 @@

; Register:    PINJ
; Description: PORT J Input Pins

.equ           PINJ       = 0x103
; Field:       PJ0
; Description: Pin J0


@@ 96,6 98,7 @@

; Register:    PORTJ
; Description: PORT J Data Register

.equ           PORTJ       = 0x105
; Field:       PJ0
; Description: Pin J0

M atmega1280/portk.asm => atmega1280/portk.asm +4 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; PORTK peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    DDRK
; Description: PORT K Data Direction Register

.equ           DDRK       = 0x107
; Field:       PK0
; Description: Pin K0


@@ 52,6 53,7 @@

; Register:    PINK
; Description: PORT K Input Pins

.equ           PINK       = 0x106
; Field:       PK0
; Description: Pin K0


@@ 96,6 98,7 @@

; Register:    PORTK
; Description: PORT K Data Register

.equ           PORTK       = 0x108
; Field:       PK0
; Description: Pin K0

M atmega1280/portl.asm => atmega1280/portl.asm +4 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; PORTL peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    DDRL
; Description: PORT L Data Direction Register

.equ           DDRL       = 0x10A
; Field:       PL0
; Description: Pin L0


@@ 52,6 53,7 @@

; Register:    PINL
; Description: PORT L Input Pins

.equ           PINL       = 0x109
; Field:       PL0
; Description: Pin L0


@@ 96,6 98,7 @@

; Register:    PORTL
; Description: PORT L Data Register

.equ           PORTL       = 0x10B
; Field:       PL0
; Description: Pin L0

M atmega1280/spi.asm => atmega1280/spi.asm +4 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; SPI peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    SPCR
; Description: SPI Control Register

.equ           SPCR       = 0x4C
; Field:       SPR
; Description: SPI Clock Rate Selects


@@ 53,10 54,12 @@

; Register:    SPDR
; Description: SPI Data Register

.equ           SPDR       = 0x4E

; Register:    SPSR
; Description: SPI Status Register

.equ           SPSR       = 0x4D
; Field:       SPI2X
; Description: Double SPI Speed Bit

M atmega1280/tc0.asm => atmega1280/tc0.asm +9 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; TC0 peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    GTCCR
; Description: General Timer/Counter Control Register

.equ           GTCCR       = 0x43
; Field:       PSRSYNC
; Description: Prescaler Reset Timer/Counter1 and Timer/Counter0


@@ 22,14 23,17 @@

; Register:    OCR0A
; Description: Timer/Counter0 Output Compare Register

.equ           OCR0A       = 0x47

; Register:    OCR0B
; Description: Timer/Counter0 Output Compare Register

.equ           OCR0B       = 0x48

; Register:    TCCR0A
; Description: Timer/Counter  Control Register A

.equ           TCCR0A       = 0x44
; Field:       WGM0
; Description: Waveform Generation Mode


@@ 63,6 67,7 @@

; Register:    TCCR0B
; Description: Timer/Counter Control Register B

.equ           TCCR0B       = 0x45
; Field:       CS0
; Description: Clock Select


@@ 97,10 102,12 @@

; Register:    TCNT0
; Description: Timer/Counter0

.equ           TCNT0       = 0x46

; Register:    TIFR0
; Description: Timer/Counter0 Interrupt Flag register

.equ           TIFR0       = 0x35
; Field:       TOV0
; Description: Timer/Counter0 Overflow Flag


@@ 120,6 127,7 @@

; Register:    TIMSK0
; Description: Timer/Counter0 Interrupt Mask Register

.equ           TIMSK0       = 0x6E
; Field:       TOIE0
; Description: Timer/Counter0 Overflow Interrupt Enable

M atmega1280/tc1.asm => atmega1280/tc1.asm +11 -1
@@ 2,28 2,33 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; TC1 peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    ICR1
; Description: Timer/Counter1 Input Capture Register  Bytes

.equ           ICR1       = 0x86

; Register:    OCR1A
; Description: Timer/Counter1 Output Compare Register A  Bytes

.equ           OCR1A       = 0x88

; Register:    OCR1B
; Description: Timer/Counter1 Output Compare Register B  Bytes

.equ           OCR1B       = 0x8A

; Register:    OCR1C
; Description: Timer/Counter1 Output Compare Register C  Bytes

.equ           OCR1C       = 0x8C

; Register:    TCCR1A
; Description: Timer/Counter1 Control Register A

.equ           TCCR1A       = 0x80
; Field:       WGM1
; Description: Waveform Generation Mode


@@ 59,6 64,7 @@

; Register:    TCCR1B
; Description: Timer/Counter1 Control Register B

.equ           TCCR1B       = 0x81
; Field:       CS1
; Description: Prescaler source of Timer/Counter 1


@@ 94,6 100,7 @@

; Register:    TCCR1C
; Description: Timer/Counter 1 Control Register C

.equ           TCCR1C       = 0x82
; Field:       FOC1C
; Description: Force Output Compare 1C


@@ 113,10 120,12 @@

; Register:    TCNT1
; Description: Timer/Counter1  Bytes

.equ           TCNT1       = 0x84

; Register:    TIFR1
; Description: Timer/Counter1 Interrupt Flag register

.equ           TIFR1       = 0x36
; Field:       TOV1
; Description: Timer/Counter1 Overflow Flag


@@ 146,6 155,7 @@

; Register:    TIMSK1
; Description: Timer/Counter1 Interrupt Mask Register

.equ           TIMSK1       = 0x6F
; Field:       TOIE1
; Description: Timer/Counter1 Overflow Interrupt Enable

M atmega1280/tc2.asm => atmega1280/tc2.asm +10 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; TC2 peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    ASSR
; Description: Asynchronous Status Register

.equ           ASSR       = 0xB6
; Field:       TCR2BUB
; Description: Timer/Counter Control Register2 Update Busy


@@ 47,6 48,7 @@

; Register:    GTCCR
; Description: General Timer Counter Control register

.equ           GTCCR       = 0x43
; Field:       PSRASY
; Description: Prescaler Reset Timer/Counter2


@@ 61,14 63,17 @@

; Register:    OCR2A
; Description: Timer/Counter2 Output Compare Register A

.equ           OCR2A       = 0xB3

; Register:    OCR2B
; Description: Timer/Counter2 Output Compare Register B

.equ           OCR2B       = 0xB4

; Register:    TCCR2A
; Description: Timer/Counter2 Control Register A

.equ           TCCR2A       = 0xB0
; Field:       WGM2
; Description: Waveform Genration Mode


@@ 102,6 107,7 @@

; Register:    TCCR2B
; Description: Timer/Counter2 Control Register B

.equ           TCCR2B       = 0xB1
; Field:       CS2
; Description: Clock Select bits


@@ 136,10 142,12 @@

; Register:    TCNT2
; Description: Timer/Counter2

.equ           TCNT2       = 0xB2

; Register:    TIFR2
; Description: Timer/Counter Interrupt Flag Register

.equ           TIFR2       = 0x37
; Field:       TOV2
; Description: Timer/Counter2 Overflow Flag


@@ 159,6 167,7 @@

; Register:    TIMSK2
; Description: Timer/Counter Interrupt Mask register

.equ           TIMSK2       = 0x70
; Field:       TOIE2
; Description: Timer/Counter2 Overflow Interrupt Enable

M atmega1280/tc3.asm => atmega1280/tc3.asm +11 -1
@@ 2,28 2,33 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; TC3 peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    ICR3
; Description: Timer/Counter3 Input Capture Register  Bytes

.equ           ICR3       = 0x96

; Register:    OCR3A
; Description: Timer/Counter3 Output Compare Register A  Bytes

.equ           OCR3A       = 0x98

; Register:    OCR3B
; Description: Timer/Counter3 Output Compare Register B  Bytes

.equ           OCR3B       = 0x9A

; Register:    OCR3C
; Description: Timer/Counter3 Output Compare Register B  Bytes

.equ           OCR3C       = 0x9C

; Register:    TCCR3A
; Description: Timer/Counter3 Control Register A

.equ           TCCR3A       = 0x90
; Field:       WGM3
; Description: Waveform Generation Mode


@@ 59,6 64,7 @@

; Register:    TCCR3B
; Description: Timer/Counter3 Control Register B

.equ           TCCR3B       = 0x91
; Field:       CS3
; Description: Prescaler source of Timer/Counter 3


@@ 94,6 100,7 @@

; Register:    TCCR3C
; Description: Timer/Counter 3 Control Register C

.equ           TCCR3C       = 0x92
; Field:       FOC3C
; Description: Force Output Compare 3C


@@ 113,10 120,12 @@

; Register:    TCNT3
; Description: Timer/Counter3  Bytes

.equ           TCNT3       = 0x94

; Register:    TIFR3
; Description: Timer/Counter3 Interrupt Flag register

.equ           TIFR3       = 0x38
; Field:       TOV3
; Description: Timer/Counter3 Overflow Flag


@@ 146,6 155,7 @@

; Register:    TIMSK3
; Description: Timer/Counter3 Interrupt Mask Register

.equ           TIMSK3       = 0x71
; Field:       TOIE3
; Description: Timer/Counter3 Overflow Interrupt Enable

M atmega1280/tc4.asm => atmega1280/tc4.asm +11 -1
@@ 2,28 2,33 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; TC4 peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    ICR4
; Description: Timer/Counter4 Input Capture Register  Bytes

.equ           ICR4       = 0xA6

; Register:    OCR4A
; Description: Timer/Counter4 Output Compare Register A  Bytes

.equ           OCR4A       = 0xA8

; Register:    OCR4B
; Description: Timer/Counter4 Output Compare Register B  Bytes

.equ           OCR4B       = 0xAA

; Register:    OCR4C
; Description: Timer/Counter4 Output Compare Register B  Bytes

.equ           OCR4C       = 0xAC

; Register:    TCCR4A
; Description: Timer/Counter4 Control Register A

.equ           TCCR4A       = 0xA0
; Field:       WGM4
; Description: Waveform Generation Mode


@@ 59,6 64,7 @@

; Register:    TCCR4B
; Description: Timer/Counter4 Control Register B

.equ           TCCR4B       = 0xA1
; Field:       CS4
; Description: Prescaler source of Timer/Counter 4


@@ 94,6 100,7 @@

; Register:    TCCR4C
; Description: Timer/Counter 4 Control Register C

.equ           TCCR4C       = 0xA2
; Field:       FOC4C
; Description: Force Output Compare 4C


@@ 113,10 120,12 @@

; Register:    TCNT4
; Description: Timer/Counter4  Bytes

.equ           TCNT4       = 0xA4

; Register:    TIFR4
; Description: Timer/Counter4 Interrupt Flag register

.equ           TIFR4       = 0x39
; Field:       TOV4
; Description: Timer/Counter4 Overflow Flag


@@ 146,6 155,7 @@

; Register:    TIMSK4
; Description: Timer/Counter4 Interrupt Mask Register

.equ           TIMSK4       = 0x72
; Field:       TOIE4
; Description: Timer/Counter4 Overflow Interrupt Enable

M atmega1280/tc5.asm => atmega1280/tc5.asm +11 -1
@@ 2,28 2,33 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; TC5 peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    ICR5
; Description: Timer/Counter5 Input Capture Register  Bytes

.equ           ICR5       = 0x126

; Register:    OCR5A
; Description: Timer/Counter5 Output Compare Register A  Bytes

.equ           OCR5A       = 0x128

; Register:    OCR5B
; Description: Timer/Counter5 Output Compare Register B  Bytes

.equ           OCR5B       = 0x12A

; Register:    OCR5C
; Description: Timer/Counter5 Output Compare Register B  Bytes

.equ           OCR5C       = 0x12C

; Register:    TCCR5A
; Description: Timer/Counter5 Control Register A

.equ           TCCR5A       = 0x120
; Field:       WGM5
; Description: Waveform Generation Mode


@@ 59,6 64,7 @@

; Register:    TCCR5B
; Description: Timer/Counter5 Control Register B

.equ           TCCR5B       = 0x121
; Field:       CS5
; Description: Prescaler source of Timer/Counter 5


@@ 94,6 100,7 @@

; Register:    TCCR5C
; Description: Timer/Counter 5 Control Register C

.equ           TCCR5C       = 0x122
; Field:       FOC5C
; Description: Force Output Compare 5C


@@ 113,10 120,12 @@

; Register:    TCNT5
; Description: Timer/Counter5  Bytes

.equ           TCNT5       = 0x124

; Register:    TIFR5
; Description: Timer/Counter5 Interrupt Flag register

.equ           TIFR5       = 0x3A
; Field:       TOV5
; Description: Timer/Counter5 Overflow Flag


@@ 146,6 155,7 @@

; Register:    TIMSK5
; Description: Timer/Counter5 Interrupt Mask Register

.equ           TIMSK5       = 0x73
; Field:       TOIE5
; Description: Timer/Counter5 Overflow Interrupt Enable

M atmega1280/twi.asm => atmega1280/twi.asm +7 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; TWI peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    TWAMR
; Description: TWI (Slave) Address Mask Register

.equ           TWAMR       = 0xBD
; Field:       TWAM
; Description: TWI (Slave) Address Mask Bits


@@ 18,6 19,7 @@

; Register:    TWAR
; Description: TWI (Slave) Address register

.equ           TWAR       = 0xBA
; Field:       TWGCE
; Description: TWI General Call Recognition Enable Bit


@@ 33,10 35,12 @@

; Register:    TWBR
; Description: TWI Bit Rate register

.equ           TWBR       = 0xB8

; Register:    TWCR
; Description: TWI Control Register

.equ           TWCR       = 0xBC
; Field:       TWIE
; Description: TWI Interrupt Enable


@@ 76,10 80,12 @@

; Register:    TWDR
; Description: TWI Data register

.equ           TWDR       = 0xBB

; Register:    TWSR
; Description: TWI Status Register

.equ           TWSR       = 0xB9
; Field:       TWPS
; Description: TWI Prescaler

M atmega1280/usart0.asm => atmega1280/usart0.asm +6 -1
@@ 2,16 2,18 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; USART0 peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    UBRR0
; Description: USART Baud Rate Register  Bytes

.equ           UBRR0       = 0xC4

; Register:    UCSR0A
; Description: USART Control and Status Register A

.equ           UCSR0A       = 0xC0
; Field:       MPCM0
; Description: Multi-processor Communication Mode


@@ 56,6 58,7 @@

; Register:    UCSR0B
; Description: USART Control and Status Register B

.equ           UCSR0B       = 0xC1
; Field:       TXB80
; Description: Transmit Data Bit 8


@@ 100,6 103,7 @@

; Register:    UCSR0C
; Description: USART Control and Status Register C

.equ           UCSR0C       = 0xC2
; Field:       UCPOL0
; Description: Clock Polarity


@@ 145,4 149,5 @@

; Register:    UDR0
; Description: USART I/O Data Register

.equ           UDR0       = 0xC6

M atmega1280/usart1.asm => atmega1280/usart1.asm +6 -1
@@ 2,16 2,18 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; USART1 peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    UBRR1
; Description: USART Baud Rate Register  Bytes

.equ           UBRR1       = 0xCC

; Register:    UCSR1A
; Description: USART Control and Status Register A

.equ           UCSR1A       = 0xC8
; Field:       MPCM1
; Description: Multi-processor Communication Mode


@@ 56,6 58,7 @@

; Register:    UCSR1B
; Description: USART Control and Status Register B

.equ           UCSR1B       = 0xC9
; Field:       TXB81
; Description: Transmit Data Bit 8


@@ 100,6 103,7 @@

; Register:    UCSR1C
; Description: USART Control and Status Register C

.equ           UCSR1C       = 0xCA
; Field:       UCPOL1
; Description: Clock Polarity


@@ 145,4 149,5 @@

; Register:    UDR1
; Description: USART I/O Data Register

.equ           UDR1       = 0xCE

M atmega1280/usart2.asm => atmega1280/usart2.asm +6 -1
@@ 2,16 2,18 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; USART2 peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    UBRR2
; Description: USART Baud Rate Register  Bytes

.equ           UBRR2       = 0xD4

; Register:    UCSR2A
; Description: USART Control and Status Register A

.equ           UCSR2A       = 0xD0
; Field:       MPCM2
; Description: Multi-processor Communication Mode


@@ 56,6 58,7 @@

; Register:    UCSR2B
; Description: USART Control and Status Register B

.equ           UCSR2B       = 0xD1
; Field:       TXB82
; Description: Transmit Data Bit 8


@@ 100,6 103,7 @@

; Register:    UCSR2C
; Description: USART Control and Status Register C

.equ           UCSR2C       = 0xD2
; Field:       UCPOL2
; Description: Clock Polarity


@@ 145,4 149,5 @@

; Register:    UDR2
; Description: USART I/O Data Register

.equ           UDR2       = 0xD6

M atmega1280/usart3.asm => atmega1280/usart3.asm +6 -1
@@ 2,16 2,18 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; USART3 peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    UBRR3
; Description: USART Baud Rate Register  Bytes

.equ           UBRR3       = 0x134

; Register:    UCSR3A
; Description: USART Control and Status Register A

.equ           UCSR3A       = 0x130
; Field:       MPCM3
; Description: Multi-processor Communication Mode


@@ 56,6 58,7 @@

; Register:    UCSR3B
; Description: USART Control and Status Register B

.equ           UCSR3B       = 0x131
; Field:       TXB83
; Description: Transmit Data Bit 8


@@ 100,6 103,7 @@

; Register:    UCSR3C
; Description: USART Control and Status Register C

.equ           UCSR3C       = 0x132
; Field:       UCPOL3
; Description: Clock Polarity


@@ 145,4 149,5 @@

; Register:    UDR3
; Description: USART I/O Data Register

.equ           UDR3       = 0x136

M atmega1280/wdt.asm => atmega1280/wdt.asm +2 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; WDT peripheral register map assembly header for ATmega1280
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    WDTCSR
; Description: Watchdog Timer Control Register

.equ           WDTCSR       = 0x60
; Field:       WDE
; Description: Watch Dog Enable

M atmega1284p/ac.asm => atmega1284p/ac.asm +4 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; AC peripheral register map assembly header for ATmega1284P
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    ACSR
; Description: Analog Comparator Control And Status Register

.equ           ACSR       = 0x50
; Field:       ACIS
; Description: Analog Comparator Interrupt Mode Select


@@ 52,6 53,7 @@

; Register:    ADCSRB
; Description: ADC Control and Status Register B

.equ           ADCSRB       = 0x7B
; Field:       ACME
; Description: Analog Comparator Multiplexer Enable


@@ 61,6 63,7 @@

; Register:    DIDR1
; Description: Digital Input Disable Register 1

.equ           DIDR1       = 0x7F
; Field:       AIN0D
; Description: AIN0 Digital Input Disable

M atmega1284p/adc.asm => atmega1284p/adc.asm +6 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; ADC peripheral register map assembly header for ATmega1284P
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    ADC
; Description: ADC Data Register Bytes

.equ           ADC       = 0x78
; Field:       ADC
; Description: ADC Data bits


@@ 18,6 19,7 @@

; Register:    ADCSRA
; Description: The ADC Control and Status register A

.equ           ADCSRA       = 0x7A
; Field:       ADPS
; Description: ADC Prescaler Select Bits


@@ 61,6 63,7 @@

; Register:    ADCSRB
; Description: The ADC Control and Status register B

.equ           ADCSRB       = 0x7B
; Field:       ADTS
; Description: ADC Auto Trigger Source bits


@@ 85,6 88,7 @@

; Register:    ADMUX
; Description: The ADC multiplexer Selection Register

.equ           ADMUX       = 0x7C
; Field:       MUX
; Description: Analog Channel and Gain Selection Bits


@@ 143,6 147,7 @@

; Register:    DIDR0
; Description: Digital Input Disable Register

.equ           DIDR0       = 0x7E
; Field:       ADC0D
; Description: No Description.

M atmega1284p/boot_load.asm => atmega1284p/boot_load.asm +2 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; BOOT_LOAD peripheral register map assembly header for ATmega1284P
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    SPMCSR
; Description: Store Program Memory Control Register

.equ           SPMCSR       = 0x57
; Field:       SPMEN
; Description: Store Program Memory Enable

M atmega1284p/cpu.asm => atmega1284p/cpu.asm +12 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; CPU peripheral register map assembly header for ATmega1284P
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    CLKPR
; Description: No Description.

.equ           CLKPR       = 0x61
; Field:       CLKPS
; Description: No Description.


@@ 33,6 34,7 @@

; Register:    GPIOR0
; Description: General Purpose IO Register 0

.equ           GPIOR0       = 0x3E
; Field:       GPIOR00
; Description: General Purpose IO Register 0 bit 0


@@ 77,6 79,7 @@

; Register:    GPIOR1
; Description: General Purpose IO Register 1

.equ           GPIOR1       = 0x4A
; Field:       GPIOR
; Description: General Purpose IO Register 1 bis


@@ 87,6 90,7 @@

; Register:    GPIOR2
; Description: General Purpose IO Register 2

.equ           GPIOR2       = 0x4B
; Field:       GPIOR
; Description: General Purpose IO Register 2 bis


@@ 97,6 101,7 @@

; Register:    MCUCR
; Description: MCU Control Register

.equ           MCUCR       = 0x55
; Field:       IVCE
; Description: Interrupt Vector Change Enable


@@ 131,6 136,7 @@

; Register:    MCUSR
; Description: MCU Status Register

.equ           MCUSR       = 0x54
; Field:       PORF
; Description: Power-on reset flag


@@ 160,6 166,7 @@

; Register:    OSCCAL
; Description: Oscillator Calibration Value

.equ           OSCCAL       = 0x66
; Field:       OSCCAL
; Description: Oscillator Calibration 


@@ 170,6 177,7 @@

; Register:    PRR0
; Description: Power Reduction Register0

.equ           PRR0       = 0x64
; Field:       PRADC
; Description: Power Reduction ADC


@@ 214,6 222,7 @@

; Register:    PRR1
; Description: Power Reduction Register1

.equ           PRR1       = 0x65
; Field:       PRTIM3
; Description: Power Reduction Timer/Counter3


@@ 223,10 232,12 @@

; Register:    RAMPZ
; Description: RAM Page Z Select Register

.equ           RAMPZ       = 0x5B

; Register:    SMCR
; Description: Sleep Mode Control Register

.equ           SMCR       = 0x53
; Field:       SE
; Description: Sleep Enable

M atmega1284p/device.asm => atmega1284p/device.asm +1 -1
@@ 2,7 2,7 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; Device definition assembly header for ATmega1284P
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; DEVICE SPECIFICATIONS
.device ATmega1284P

M atmega1284p/eeprom.asm => atmega1284p/eeprom.asm +4 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; EEPROM peripheral register map assembly header for ATmega1284P
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    EEAR
; Description: EEPROM Address Register Low Bytes

.equ           EEAR       = 0x41
; Field:       EEAR
; Description: EEPROM Address bits


@@ 18,6 19,7 @@

; Register:    EECR
; Description: EEPROM Control Register

.equ           EECR       = 0x3F
; Field:       EERE
; Description: EEPROM Read Enable


@@ 52,6 54,7 @@

; Register:    EEDR
; Description: EEPROM Data Register

.equ           EEDR       = 0x40
; Field:       EEDR
; Description: EEPROM Data bits

M atmega1284p/exint.asm => atmega1284p/exint.asm +10 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; EXINT peripheral register map assembly header for ATmega1284P
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    EICRA
; Description: External Interrupt Control Register A

.equ           EICRA       = 0x69
; Field:       ISC0
; Description: External Interrupt Sense Control Bit


@@ 45,6 46,7 @@

; Register:    EIFR
; Description: External Interrupt Flag Register

.equ           EIFR       = 0x3C
; Field:       INTF0
; Description: External Interrupt Flags 0


@@ 64,6 66,7 @@

; Register:    EIMSK
; Description: External Interrupt Mask Register

.equ           EIMSK       = 0x3D
; Field:       INT0
; Description: External Interrupt 0 Request Enable


@@ 83,6 86,7 @@

; Register:    PCICR
; Description: Pin Change Interrupt Control Register

.equ           PCICR       = 0x68
; Field:       PCIE0
; Description: Pin Change Interrupt Enable 0


@@ 107,6 111,7 @@

; Register:    PCIFR
; Description: Pin Change Interrupt Flag Register

.equ           PCIFR       = 0x3B
; Field:       PCIF0
; Description: Pin Change Interrupt Flag 0


@@ 131,6 136,7 @@

; Register:    PCMSK0
; Description: Pin Change Mask Register 0

.equ           PCMSK0       = 0x6B
; Field:       PCINT
; Description: Pin Change Enable Masks


@@ 141,6 147,7 @@

; Register:    PCMSK1
; Description: Pin Change Mask Register 1

.equ           PCMSK1       = 0x6C
; Field:       PCINT
; Description: Pin Change Enable Masks


@@ 151,6 158,7 @@

; Register:    PCMSK2
; Description: Pin Change Mask Register 2

.equ           PCMSK2       = 0x6D
; Field:       PCINT
; Description: Pin Change Enable Masks


@@ 161,6 169,7 @@

; Register:    PCMSK3
; Description: Pin Change Mask Register 3

.equ           PCMSK3       = 0x73
; Field:       PCINT
; Description: Pin Change Enable Masks

M atmega1284p/fuse.asm => atmega1284p/fuse.asm +4 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; FUSE peripheral register map assembly header for ATmega1284P
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    EXTENDED
; Description: No Description.

.equ           EXTENDED       = 0x02
; Field:       BODLEVEL
; Description: Brown-out Detector trigger level


@@ 23,6 24,7 @@

; Register:    HIGH
; Description: No Description.

.equ           HIGH       = 0x01
; Field:       BOOTRST
; Description: Boot Reset vector Enabled


@@ 68,6 70,7 @@

; Register:    LOW
; Description: No Description.

.equ           LOW       = 0x00
; Field:       SUT_CKSEL
; Description: Select Clock Source

M atmega1284p/jtag.asm => atmega1284p/jtag.asm +4 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; JTAG peripheral register map assembly header for ATmega1284P
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    MCUCR
; Description: MCU Control Register

.equ           MCUCR       = 0x55
; Field:       JTD
; Description: JTAG Interface Disable


@@ 17,6 18,7 @@

; Register:    MCUSR
; Description: MCU Status Register

.equ           MCUSR       = 0x54
; Field:       JTRF
; Description: JTAG Reset Flag


@@ 26,4 28,5 @@

; Register:    OCDR
; Description: On-Chip Debug Related Register in I/O Memory

.equ           OCDR       = 0x51

M atmega1284p/lockbit.asm => atmega1284p/lockbit.asm +2 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; LOCKBIT peripheral register map assembly header for ATmega1284P
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    LOCKBIT
; Description: No Description.

.equ           LOCKBIT       = 0x00
; Field:       LB
; Description: Memory Lock

M atmega1284p/porta.asm => atmega1284p/porta.asm +4 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; PORTA peripheral register map assembly header for ATmega1284P
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    DDRA
; Description: Port A Data Direction Register

.equ           DDRA       = 0x21
; Field:       PA0
; Description: Pin A0


@@ 52,6 53,7 @@

; Register:    PINA
; Description: Port A Input Pins

.equ           PINA       = 0x20
; Field:       PA0
; Description: Pin A0


@@ 96,6 98,7 @@

; Register:    PORTA
; Description: Port A Data Register

.equ           PORTA       = 0x22
; Field:       PA0
; Description: Pin A0

M atmega1284p/portb.asm => atmega1284p/portb.asm +4 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; PORTB peripheral register map assembly header for ATmega1284P
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    DDRB
; Description: Port B Data Direction Register

.equ           DDRB       = 0x24
; Field:       PB0
; Description: Pin B0


@@ 52,6 53,7 @@

; Register:    PINB
; Description: Port B Input Pins

.equ           PINB       = 0x23
; Field:       PB0
; Description: Pin B0


@@ 96,6 98,7 @@

; Register:    PORTB
; Description: Port B Data Register

.equ           PORTB       = 0x25
; Field:       PB0
; Description: Pin B0

M atmega1284p/portc.asm => atmega1284p/portc.asm +4 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; PORTC peripheral register map assembly header for ATmega1284P
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    DDRC
; Description: Port C Data Direction Register

.equ           DDRC       = 0x27
; Field:       PC0
; Description: Pin C0


@@ 52,6 53,7 @@

; Register:    PINC
; Description: Port C Input Pins

.equ           PINC       = 0x26
; Field:       PC0
; Description: Pin C0


@@ 96,6 98,7 @@

; Register:    PORTC
; Description: Port C Data Register

.equ           PORTC       = 0x28
; Field:       PC0
; Description: Pin C0

M atmega1284p/portd.asm => atmega1284p/portd.asm +4 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; PORTD peripheral register map assembly header for ATmega1284P
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    DDRD
; Description: Port D Data Direction Register

.equ           DDRD       = 0x2A
; Field:       PD0
; Description: Pin D0


@@ 52,6 53,7 @@

; Register:    PIND
; Description: Port D Input Pins

.equ           PIND       = 0x29
; Field:       PD0
; Description: Pin D0


@@ 96,6 98,7 @@

; Register:    PORTD
; Description: Port D Data Register

.equ           PORTD       = 0x2B
; Field:       PD0
; Description: Pin D0

M atmega1284p/spi.asm => atmega1284p/spi.asm +4 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; SPI peripheral register map assembly header for ATmega1284P
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    SPCR
; Description: SPI Control Register

.equ           SPCR       = 0x4C
; Field:       SPR
; Description: SPI Clock Rate Selects


@@ 53,6 54,7 @@

; Register:    SPDR
; Description: SPI Data Register

.equ           SPDR       = 0x4E
; Field:       SPD
; Description: SPI Data bits


@@ 63,6 65,7 @@

; Register:    SPSR
; Description: SPI Status Register

.equ           SPSR       = 0x4D
; Field:       SPI2X
; Description: Double SPI Speed Bit

M atmega1284p/tc0.asm => atmega1284p/tc0.asm +9 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; TC0 peripheral register map assembly header for ATmega1284P
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    GTCCR
; Description: General Timer/Counter Control Register

.equ           GTCCR       = 0x43
; Field:       PSRSYNC
; Description: Prescaler Reset Timer/Counter1 and Timer/Counter0


@@ 22,6 23,7 @@

; Register:    OCR0A
; Description: Timer/Counter0 Output Compare Register A

.equ           OCR0A       = 0x47
; Field:       OCR0A
; Description: Timer/Counter0 Output Compare A bits


@@ 32,6 34,7 @@

; Register:    OCR0B
; Description: Timer/Counter0 Output Compare Register B

.equ           OCR0B       = 0x48
; Field:       OCR0B
; Description: Timer/Counter0 Output Compare B bits


@@ 42,6 45,7 @@

; Register:    TCCR0A
; Description: Timer/Counter Control Register A

.equ           TCCR0A       = 0x44
; Field:       WGM0
; Description: Waveform Generation Mode


@@ 75,6 79,7 @@

; Register:    TCCR0B
; Description: Timer/Counter Control Register B

.equ           TCCR0B       = 0x45
; Field:       CS0
; Description: Clock Select


@@ 109,6 114,7 @@

; Register:    TCNT0
; Description: Timer/Counter0

.equ           TCNT0       = 0x46
; Field:       TCNT0
; Description: Timer/Counter0 bits


@@ 119,6 125,7 @@

; Register:    TIFR0
; Description: Timer/Counter0 Interrupt Flag register

.equ           TIFR0       = 0x35
; Field:       TOV0
; Description: Timer/Counter0 Overflow Flag


@@ 138,6 145,7 @@

; Register:    TIMSK0
; Description: Timer/Counter0 Interrupt Mask Register

.equ           TIMSK0       = 0x6E
; Field:       TOIE0
; Description: Timer/Counter0 Overflow Interrupt Enable

M atmega1284p/tc1.asm => atmega1284p/tc1.asm +10 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; TC1 peripheral register map assembly header for ATmega1284P
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    ICR1
; Description: Timer/Counter1 Input Capture Register Bytes

.equ           ICR1       = 0x86
; Field:       ICR1
; Description: Timer/Counter1 Input Capture bits


@@ 18,6 19,7 @@

; Register:    OCR1A
; Description: Timer/Counter1 Output Compare Register A Bytes

.equ           OCR1A       = 0x88
; Field:       OCR1A
; Description: Timer/Counter1 Output Compare A bits


@@ 28,6 30,7 @@

; Register:    OCR1B
; Description: Timer/Counter1 Output Compare Register B Bytes

.equ           OCR1B       = 0x8A
; Field:       OCR1B
; Description: Timer/Counter1 Output Compare B bits


@@ 38,6 41,7 @@

; Register:    TCCR1A
; Description: Timer/Counter1 Control Register A

.equ           TCCR1A       = 0x80
; Field:       WGM1
; Description: Pulse Width Modulator Select Bits


@@ 66,6 70,7 @@

; Register:    TCCR1B
; Description: Timer/Counter1 Control Register B

.equ           TCCR1B       = 0x81
; Field:       CS1
; Description: Clock Select1 bits


@@ 101,6 106,7 @@

; Register:    TCCR1C
; Description: Timer/Counter1 Control Register C

.equ           TCCR1C       = 0x82
; Field:       FOC1B
; Description: Force Output Compare for Channel B


@@ 115,6 121,7 @@

; Register:    TCNT1
; Description: Timer/Counter1 Bytes

.equ           TCNT1       = 0x84
; Field:       TCNT1
; Description: Timer/Counter1 bits


@@ 125,6 132,7 @@

; Register:    TIFR1
; Description: Timer/Counter Interrupt Flag register

.equ           TIFR1       = 0x36
; Field:       TOV1
; Description: Timer/Counter1 Overflow Flag


@@ 149,6 157,7 @@

; Register:    TIMSK1
; Description: Timer/Counter1 Interrupt Mask Register

.equ           TIMSK1       = 0x6F
; Field:       TOIE1
; Description: Timer/Counter1 Overflow Interrupt Enable

M atmega1284p/tc2.asm => atmega1284p/tc2.asm +10 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; TC2 peripheral register map assembly header for ATmega1284P
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    ASSR
; Description: Asynchronous Status Register

.equ           ASSR       = 0xB6
; Field:       TCR2BUB
; Description: Timer/Counter Control Register2 Update Busy


@@ 47,6 48,7 @@

; Register:    GTCCR
; Description: General Timer Counter Control register

.equ           GTCCR       = 0x43
; Field:       PSRASY
; Description: Prescaler Reset Timer/Counter2


@@ 61,6 63,7 @@

; Register:    OCR2A
; Description: Timer/Counter2 Output Compare Register A

.equ           OCR2A       = 0xB3
; Field:       OCR2A
; Description: Timer/Counter2 Output Compare A bits


@@ 71,6 74,7 @@

; Register:    OCR2B
; Description: Timer/Counter2 Output Compare Register B

.equ           OCR2B       = 0xB4
; Field:       OCR2B
; Description: Timer/Counter2 Output Compare B bits


@@ 81,6 85,7 @@

; Register:    TCCR2A
; Description: Timer/Counter2 Control Register A

.equ           TCCR2A       = 0xB0
; Field:       WGM2
; Description: Waveform Genration Mode


@@ 114,6 119,7 @@

; Register:    TCCR2B
; Description: Timer/Counter2 Control Register B

.equ           TCCR2B       = 0xB1
; Field:       CS2
; Description: Clock Select bits


@@ 148,6 154,7 @@

; Register:    TCNT2
; Description: Timer/Counter2

.equ           TCNT2       = 0xB2
; Field:       TCNT2
; Description: Timer/Counter2 bits


@@ 158,6 165,7 @@

; Register:    TIFR2
; Description: Timer/Counter Interrupt Flag Register

.equ           TIFR2       = 0x37
; Field:       TOV2
; Description: Timer/Counter2 Overflow Flag


@@ 177,6 185,7 @@

; Register:    TIMSK2
; Description: Timer/Counter Interrupt Mask register

.equ           TIMSK2       = 0x70
; Field:       TOIE2
; Description: Timer/Counter2 Overflow Interrupt Enable

M atmega1284p/tc3.asm => atmega1284p/tc3.asm +10 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; TC3 peripheral register map assembly header for ATmega1284P
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    ICR3
; Description: Timer/Counter3 Input Capture Register Bytes

.equ           ICR3       = 0x96
; Field:       ICR3
; Description: Timer/Counter3 Input Capture bits


@@ 18,6 19,7 @@

; Register:    OCR3A
; Description: Timer/Counter3 Output Compare Register A Bytes

.equ           OCR3A       = 0x98
; Field:       OCR3A
; Description: Timer/Counter3 Output Compare A bits


@@ 28,6 30,7 @@

; Register:    OCR3B
; Description: Timer/Counter3 Output Compare Register B Bytes

.equ           OCR3B       = 0x9A
; Field:       OCR3B
; Description: Timer/Counter3 Output Compare B bits


@@ 38,6 41,7 @@

; Register:    TCCR3A
; Description: Timer/Counter3 Control Register A

.equ           TCCR3A       = 0x90
; Field:       WGM3
; Description: Pulse Width Modulator Select Bits


@@ 66,6 70,7 @@

; Register:    TCCR3B
; Description: Timer/Counter3 Control Register B

.equ           TCCR3B       = 0x91
; Field:       CS3
; Description: Clock Select3 bits


@@ 101,6 106,7 @@

; Register:    TCCR3C
; Description: Timer/Counter3 Control Register C

.equ           TCCR3C       = 0x92
; Field:       FOC3B
; Description: Force Output Compare for Channel B


@@ 115,6 121,7 @@

; Register:    TCNT3
; Description: Timer/Counter3 Bytes

.equ           TCNT3       = 0x94
; Field:       TCNT3
; Description: Timer/Counter3 bits


@@ 125,6 132,7 @@

; Register:    TIFR3
; Description: Timer/Counter Interrupt Flag register

.equ           TIFR3       = 0x38
; Field:       TOV3
; Description: Timer/Counter3 Overflow Flag


@@ 149,6 157,7 @@

; Register:    TIMSK3
; Description: Timer/Counter3 Interrupt Mask Register

.equ           TIMSK3       = 0x71
; Field:       TOIE3
; Description: Timer/Counter3 Overflow Interrupt Enable

M atmega1284p/twi.asm => atmega1284p/twi.asm +7 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; TWI peripheral register map assembly header for ATmega1284P
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    TWAMR
; Description: TWI (Slave) Address Mask Register

.equ           TWAMR       = 0xBD
; Field:       TWAM
; Description: TWI (Slave) Address Mask Bits


@@ 18,6 19,7 @@

; Register:    TWAR
; Description: TWI (Slave) Address register

.equ           TWAR       = 0xBA
; Field:       TWGCE
; Description: TWI General Call Recognition Enable Bit


@@ 33,6 35,7 @@

; Register:    TWBR
; Description: TWI Bit Rate register

.equ           TWBR       = 0xB8
; Field:       TWBR
; Description: TWI Bit Rate bits


@@ 43,6 46,7 @@

; Register:    TWCR
; Description: TWI Control Register

.equ           TWCR       = 0xBC
; Field:       TWIE
; Description: TWI Interrupt Enable


@@ 82,6 86,7 @@

; Register:    TWDR
; Description: TWI Data register

.equ           TWDR       = 0xBB
; Field:       TWD
; Description: TWI Data bits


@@ 92,6 97,7 @@

; Register:    TWSR
; Description: TWI Status Register

.equ           TWSR       = 0xB9
; Field:       TWPS
; Description: TWI Prescaler

M atmega1284p/usart0.asm => atmega1284p/usart0.asm +6 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; USART0 peripheral register map assembly header for ATmega1284P
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    UBRR0
; Description: USART Baud Rate Register Bytes

.equ           UBRR0       = 0xC4
; Field:       UBRR0
; Description: USART Baud Rate Register


@@ 18,6 19,7 @@

; Register:    UCSR0A
; Description: USART Control and Status Register A

.equ           UCSR0A       = 0xC0
; Field:       MPCM0
; Description: Multi-processor Communication Mode


@@ 62,6 64,7 @@

; Register:    UCSR0B
; Description: USART Control and Status Register B

.equ           UCSR0B       = 0xC1
; Field:       TXB80
; Description: Transmit Data Bit 8


@@ 106,6 109,7 @@

; Register:    UCSR0C
; Description: USART Control and Status Register C

.equ           UCSR0C       = 0xC2
; Field:       UCPOL0
; Description: Clock Polarity


@@ 151,6 155,7 @@

; Register:    UDR0
; Description: USART I/O Data Register

.equ           UDR0       = 0xC6
; Field:       UDR0
; Description: USART I/O Data bits

M atmega1284p/usart1.asm => atmega1284p/usart1.asm +6 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; USART1 peripheral register map assembly header for ATmega1284P
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    UBRR1
; Description: USART Baud Rate Register Bytes

.equ           UBRR1       = 0xCC
; Field:       UBRR1
; Description: USART Baud Rate Register


@@ 18,6 19,7 @@

; Register:    UCSR1A
; Description: USART Control and Status Register A

.equ           UCSR1A       = 0xC8
; Field:       MPCM1
; Description: Multi-processor Communication Mode


@@ 62,6 64,7 @@

; Register:    UCSR1B
; Description: USART Control and Status Register B

.equ           UCSR1B       = 0xC9
; Field:       TXB81
; Description: Transmit Data Bit 8


@@ 106,6 109,7 @@

; Register:    UCSR1C
; Description: USART Control and Status Register C

.equ           UCSR1C       = 0xCA
; Field:       UCPOL1
; Description: Clock Polarity


@@ 151,6 155,7 @@

; Register:    UDR1
; Description: USART I/O Data Register

.equ           UDR1       = 0xCE
; Field:       UDR1
; Description: USART I/O Data bits

M atmega1284p/wdt.asm => atmega1284p/wdt.asm +2 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; WDT peripheral register map assembly header for ATmega1284P
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    WDTCSR
; Description: Watchdog Timer Control Register

.equ           WDTCSR       = 0x60
; Field:       WDE
; Description: Watch Dog Enable

M atmega128rfa1/ac.asm => atmega128rfa1/ac.asm +4 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; AC peripheral register map assembly header for ATmega128RFA1
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    ACSR
; Description: Analog Comparator Control And Status Register

.equ           ACSR       = 0x50
; Field:       ACIS
; Description: Analog Comparator Interrupt Mode Select


@@ 53,6 54,7 @@

; Register:    ADCSRB
; Description: ADC Control and Status Register B

.equ           ADCSRB       = 0x7B
; Field:       ACME
; Description: Analog Comparator Multiplexer Enable


@@ 62,6 64,7 @@

; Register:    DIDR1
; Description: Digital Input Disable Register 1

.equ           DIDR1       = 0x7F
; Field:       AIN0D
; Description: AIN0 Digital Input Disable

M atmega128rfa1/adc.asm => atmega128rfa1/adc.asm +8 -1
@@ 2,16 2,18 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; ADC peripheral register map assembly header for ATmega128RFA1
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    ADC
; Description: ADC Data Register  Bytes

.equ           ADC       = 0x78

; Register:    ADCSRA
; Description: The ADC Control and Status Register A

.equ           ADCSRA       = 0x7A
; Field:       ADPS
; Description: ADC  Prescaler Select Bits


@@ 55,6 57,7 @@

; Register:    ADCSRB
; Description: The ADC Control and Status Register B

.equ           ADCSRB       = 0x7B
; Field:       ADTS
; Description: ADC Auto Trigger Source


@@ 99,6 102,7 @@

; Register:    ADCSRC
; Description: The ADC Control and Status Register C

.equ           ADCSRC       = 0x77
; Field:       ADSUT
; Description: ADC Start-up Time


@@ 131,6 135,7 @@

; Register:    ADMUX
; Description: The ADC Multiplexer Selection Register

.equ           ADMUX       = 0x7C
; Field:       MUX
; Description: Analog Channel and Gain Selection Bits


@@ 156,6 161,7 @@

; Register:    DIDR0
; Description: Digital Input Disable Register 0

.equ           DIDR0       = 0x7E
; Field:       ADC0D
; Description: Disable ADC7:0 Digital Input


@@ 200,6 206,7 @@

; Register:    DIDR2
; Description: Digital Input Disable Register 2

.equ           DIDR2       = 0x7D
; Field:       ADC8D
; Description: Reserved Bits

M atmega128rfa1/boot_load.asm => atmega128rfa1/boot_load.asm +2 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; BOOT_LOAD peripheral register map assembly header for ATmega128RFA1
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    SPMCSR
; Description: Store Program Memory Control Register

.equ           SPMCSR       = 0x57
; Field:       SPMEN
; Description: Store Program Memory Enable

M atmega128rfa1/cpu.asm => atmega128rfa1/cpu.asm +13 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; CPU peripheral register map assembly header for ATmega128RFA1
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    CLKPR
; Description: Clock Prescale Register

.equ           CLKPR       = 0x61
; Field:       CLKPS
; Description: Clock Prescaler Select Bits


@@ 41,6 42,7 @@

; Register:    GPIOR0
; Description: General Purpose IO Register 0

.equ           GPIOR0       = 0x3E
; Field:       GPIOR00
; Description: General Purpose I/O Register 0 Value


@@ 85,6 87,7 @@

; Register:    GPIOR1
; Description: General Purpose IO Register 1

.equ           GPIOR1       = 0x4A
; Field:       GPIOR
; Description: General Purpose I/O Register 1 Value


@@ 95,6 98,7 @@

; Register:    GPIOR2
; Description: General Purpose I/O Register 2

.equ           GPIOR2       = 0x4B
; Field:       GPIOR
; Description: General Purpose I/O Register 2 Value


@@ 105,6 109,7 @@

; Register:    MCUCR
; Description: MCU Control Register

.equ           MCUCR       = 0x55
; Field:       IVCE
; Description: Interrupt Vector Change Enable


@@ 129,6 134,7 @@

; Register:    MCUSR
; Description: MCU Status Register

.equ           MCUSR       = 0x54
; Field:       PORF
; Description: Power-on Reset Flag


@@ 164,6 170,7 @@

; Register:    OSCCAL
; Description: Oscillator Calibration Value

.equ           OSCCAL       = 0x66
; Field:       CAL
; Description: Oscillator Calibration Tuning Value


@@ 185,6 192,7 @@

; Register:    PRR0
; Description: Power Reduction Register0

.equ           PRR0       = 0x64
; Field:       PRADC
; Description: Power Reduction ADC


@@ 229,6 237,7 @@

; Register:    PRR1
; Description: Power Reduction Register 1

.equ           PRR1       = 0x65
; Field:       PRUSART1
; Description: Power Reduction USART1


@@ 258,6 267,7 @@

; Register:    PRR2
; Description: Power Reduction Register 2

.equ           PRR2       = 0x63
; Field:       PRRAM0
; Description: Power Reduction SRAM0


@@ 282,6 292,7 @@

; Register:    RAMPZ
; Description: Extended Z-pointer Register for ELPM/SPM

.equ           RAMPZ       = 0x5B
; Field:       RAMPZ
; Description: Extended Z-Pointer Value


@@ 300,6 311,7 @@

; Register:    SMCR
; Description: Sleep Mode Control Register

.equ           SMCR       = 0x53
; Field:       SE
; Description: Sleep Enable

M atmega128rfa1/device.asm => atmega128rfa1/device.asm +1 -1
@@ 2,7 2,7 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; Device definition assembly header for ATmega128RFA1
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; DEVICE SPECIFICATIONS
.device ATmega128RFA1

M atmega128rfa1/eeprom.asm => atmega128rfa1/eeprom.asm +4 -1
@@ 2,16 2,18 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; EEPROM peripheral register map assembly header for ATmega128RFA1
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    EEAR
; Description: EEPROM Address Register  Bytes

.equ           EEAR       = 0x41

; Register:    EECR
; Description: EEPROM Control Register

.equ           EECR       = 0x3F
; Field:       EERE
; Description: EEPROM Read Enable


@@ 53,4 55,5 @@

; Register:    EEDR
; Description: EEPROM Data Register

.equ           EEDR       = 0x40

M atmega128rfa1/exint.asm => atmega128rfa1/exint.asm +10 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; EXINT peripheral register map assembly header for ATmega128RFA1
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    EICRA
; Description: External Interrupt Control Register A

.equ           EICRA       = 0x69
; Field:       ISC0
; Description: External Interrupt 0 Sense Control Bit


@@ 56,6 57,7 @@

; Register:    EICRB
; Description: External Interrupt Control Register B

.equ           EICRB       = 0x6A
; Field:       ISC4
; Description: External Interrupt 4 Sense Control Bit


@@ 104,6 106,7 @@

; Register:    EIFR
; Description: External Interrupt Flag Register

.equ           EIFR       = 0x3C
; Field:       INTF
; Description: External Interrupt Flag


@@ 119,6 122,7 @@

; Register:    EIMSK
; Description: External Interrupt Mask Register

.equ           EIMSK       = 0x3D
; Field:       INT
; Description: External Interrupt Request Enable


@@ 132,6 136,7 @@

; Register:    PCICR
; Description: Pin Change Interrupt Control Register

.equ           PCICR       = 0x68
; Field:       PCIE
; Description: Pin Change Interrupt Enables


@@ 148,6 153,7 @@

; Register:    PCIFR
; Description: Pin Change Interrupt Flag Register

.equ           PCIFR       = 0x3B
; Field:       PCIF
; Description: Pin Change Interrupt Flags


@@ 164,10 170,12 @@

; Register:    PCMSK0
; Description: Pin Change Mask Register 0

.equ           PCMSK0       = 0x6B

; Register:    PCMSK1
; Description: Pin Change Mask Register 1

.equ           PCMSK1       = 0x6C
; Field:       PCINT
; Description: Pin Change Enable Mask


@@ 178,6 186,7 @@

; Register:    PCMSK2
; Description: Pin Change Mask Register 2

.equ           PCMSK2       = 0x6D
; Field:       PCINT
; Description: Pin Change Enable Mask

M atmega128rfa1/flash.asm => atmega128rfa1/flash.asm +3 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; FLASH peripheral register map assembly header for ATmega128RFA1
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    BGCR
; Description: Reference Voltage Calibration Register

.equ           BGCR       = 0x67
; Field:       BGCAL
; Description: Coarse Calibration Bits


@@ 41,6 42,7 @@

; Register:    NEMCR
; Description: Flash Extended-Mode Control-Register

.equ           NEMCR       = 0x75
; Field:       AEAM
; Description: Address for Extended Address Mode of Extra Rows

M atmega128rfa1/fuse.asm => atmega128rfa1/fuse.asm +4 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; FUSE peripheral register map assembly header for ATmega128RFA1
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    EXTENDED
; Description: No Description.

.equ           EXTENDED       = 0x02
; Field:       BODLEVEL
; Description: Brown-out Detector trigger level


@@ 27,6 28,7 @@

; Register:    HIGH
; Description: No Description.

.equ           HIGH       = 0x01
; Field:       BOOTRST
; Description: Boot Reset vector Enabled


@@ 72,6 74,7 @@

; Register:    LOW
; Description: No Description.

.equ           LOW       = 0x00
; Field:       CKSEL_SUT
; Description: Select Clock Source : Start-up time

M atmega128rfa1/jtag.asm => atmega128rfa1/jtag.asm +4 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; JTAG peripheral register map assembly header for ATmega128RFA1
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    MCUCR
; Description: MCU Control Register

.equ           MCUCR       = 0x55
; Field:       JTD
; Description: JTAG Interface Disable


@@ 17,6 18,7 @@

; Register:    MCUSR
; Description: MCU Status Register

.equ           MCUSR       = 0x54
; Field:       JTRF
; Description: JTAG Reset Flag


@@ 26,6 28,7 @@

; Register:    OCDR
; Description: On-Chip Debug Register

.equ           OCDR       = 0x51
; Field:       OCDR
; Description: On-Chip Debug Register Data

M atmega128rfa1/lockbit.asm => atmega128rfa1/lockbit.asm +2 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; LOCKBIT peripheral register map assembly header for ATmega128RFA1
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    LOCKBIT
; Description: No Description.

.equ           LOCKBIT       = 0x00
; Field:       LB
; Description: Memory Lock

M atmega128rfa1/porta.asm => atmega128rfa1/porta.asm +4 -1
@@ 2,18 2,21 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; PORTA peripheral register map assembly header for ATmega128RFA1
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    DDRA
; Description: Port A Data Direction Register

.equ           DDRA       = 0x21

; Register:    PINA
; Description: Port A Input Pins Address

.equ           PINA       = 0x20

; Register:    PORTA
; Description: Port A Data Register

.equ           PORTA       = 0x22

M atmega128rfa1/portb.asm => atmega128rfa1/portb.asm +4 -1
@@ 2,18 2,21 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; PORTB peripheral register map assembly header for ATmega128RFA1
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    DDRB
; Description: Port B Data Direction Register

.equ           DDRB       = 0x24

; Register:    PINB
; Description: Port B Input Pins Address

.equ           PINB       = 0x23

; Register:    PORTB
; Description: Port B Data Register

.equ           PORTB       = 0x25

M atmega128rfa1/portc.asm => atmega128rfa1/portc.asm +4 -1
@@ 2,18 2,21 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; PORTC peripheral register map assembly header for ATmega128RFA1
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    DDRC
; Description: Port C Data Direction Register

.equ           DDRC       = 0x27

; Register:    PINC
; Description: Port C Input Pins Address

.equ           PINC       = 0x26

; Register:    PORTC
; Description: Port C Data Register

.equ           PORTC       = 0x28

M atmega128rfa1/portd.asm => atmega128rfa1/portd.asm +4 -1
@@ 2,18 2,21 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; PORTD peripheral register map assembly header for ATmega128RFA1
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    DDRD
; Description: Port D Data Direction Register

.equ           DDRD       = 0x2A

; Register:    PIND
; Description: Port D Input Pins Address

.equ           PIND       = 0x29

; Register:    PORTD
; Description: Port D Data Register

.equ           PORTD       = 0x2B

M atmega128rfa1/porte.asm => atmega128rfa1/porte.asm +4 -1
@@ 2,18 2,21 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; PORTE peripheral register map assembly header for ATmega128RFA1
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    DDRE
; Description: Port E Data Direction Register

.equ           DDRE       = 0x2D

; Register:    PINE
; Description: Port E Input Pins Address

.equ           PINE       = 0x2C

; Register:    PORTE
; Description: Port E Data Register

.equ           PORTE       = 0x2E

M atmega128rfa1/portf.asm => atmega128rfa1/portf.asm +4 -1
@@ 2,18 2,21 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; PORTF peripheral register map assembly header for ATmega128RFA1
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    DDRF
; Description: Port F Data Direction Register

.equ           DDRF       = 0x30

; Register:    PINF
; Description: Port F Input Pins Address

.equ           PINF       = 0x2F

; Register:    PORTF
; Description: Port F Data Register

.equ           PORTF       = 0x31

M atmega128rfa1/portg.asm => atmega128rfa1/portg.asm +4 -1
@@ 2,18 2,21 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; PORTG peripheral register map assembly header for ATmega128RFA1
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    DDRG
; Description: Port G Data Direction Register

.equ           DDRG       = 0x33

; Register:    PING
; Description: Port G Input Pins Address

.equ           PING       = 0x32

; Register:    PORTG
; Description: Port G Data Register

.equ           PORTG       = 0x34

M atmega128rfa1/pwrctrl.asm => atmega128rfa1/pwrctrl.asm +12 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; PWRCTRL peripheral register map assembly header for ATmega128RFA1
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    DPDS0
; Description: Port Driver Strength Register 0

.equ           DPDS0       = 0x136
; Field:       PBDRV
; Description: Driver Strength Port B


@@ 56,6 57,7 @@

; Register:    DPDS1
; Description: Port Driver Strength Register 1

.equ           DPDS1       = 0x137
; Field:       PGDRV
; Description: Driver Strength Port G


@@ 77,6 79,7 @@

; Register:    DRTRAM0
; Description: Data Retention Configuration Register of SRAM 0

.equ           DRTRAM0       = 0x135
; Field:       ENDRT
; Description: Enable SRAM Data Retention


@@ 97,6 100,7 @@

; Register:    DRTRAM1
; Description: Data Retention Configuration Register of SRAM 1

.equ           DRTRAM1       = 0x134
; Field:       ENDRT
; Description: Enable SRAM Data Retention


@@ 117,6 121,7 @@

; Register:    DRTRAM2
; Description: Data Retention Configuration Register of SRAM 2

.equ           DRTRAM2       = 0x133
; Field:       ENDRT
; Description: Enable SRAM Data Retention


@@ 136,6 141,7 @@

; Register:    DRTRAM3
; Description: Data Retention Configuration Register of SRAM 3

.equ           DRTRAM3       = 0x132
; Field:       ENDRT
; Description: Enable SRAM Data Retention


@@ 156,6 162,7 @@

; Register:    LLCR
; Description: Low Leakage Voltage Regulator Control Register

.equ           LLCR       = 0x12F
; Field:       LLENCAL
; Description: Enable Automatic Calibration


@@ 196,6 203,7 @@

; Register:    LLDRH
; Description: Low Leakage Voltage Regulator Data Register (High-Byte)

.equ           LLDRH       = 0x131
; Field:       LLDRH
; Description: High-Byte Data Register Bits


@@ 215,6 223,7 @@

; Register:    LLDRL
; Description: Low Leakage Voltage Regulator Data Register (Low-Byte)

.equ           LLDRL       = 0x130
; Field:       LLDRL
; Description: Low-Byte Data Register Bits


@@ 234,6 243,7 @@

; Register:    MCUCR
; Description: MCU Control Register

.equ           MCUCR       = 0x55
; Field:       PUD
; Description: Pull-up Disable


@@ 243,6 253,7 @@

; Register:    TRXPR
; Description: Transceiver Pin Register

.equ           TRXPR       = 0x139
; Field:       TRXRST
; Description: Force Transceiver Reset

M atmega128rfa1/spi.asm => atmega128rfa1/spi.asm +4 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; SPI peripheral register map assembly header for ATmega128RFA1
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    SPCR
; Description: SPI Control Register

.equ           SPCR       = 0x4C
; Field:       SPR
; Description: SPI Clock Rate Select 1 and 0


@@ 53,10 54,12 @@

; Register:    SPDR
; Description: SPI Data Register

.equ           SPDR       = 0x4E

; Register:    SPSR
; Description: SPI Status Register

.equ           SPSR       = 0x4D
; Field:       SPI2X
; Description: Double SPI Speed Bit

M atmega128rfa1/symcnt.asm => atmega128rfa1/symcnt.asm +30 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; SYMCNT peripheral register map assembly header for ATmega128RFA1
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    SCBTSRHH
; Description: Symbol Counter Beacon Timestamp Register HH-Byte

.equ           SCBTSRHH       = 0xE8
; Field:       SCBTSRHH
; Description: Symbol Counter Beacon Timestamp Register HH-Byte


@@ 18,6 19,7 @@

; Register:    SCBTSRHL
; Description: Symbol Counter Beacon Timestamp Register HL-Byte

.equ           SCBTSRHL       = 0xE7
; Field:       SCBTSRHL
; Description: Symbol Counter Beacon Timestamp Register HL-Byte


@@ 28,6 30,7 @@

; Register:    SCBTSRLH
; Description: Symbol Counter Beacon Timestamp Register LH-Byte

.equ           SCBTSRLH       = 0xE6
; Field:       SCBTSRLH
; Description: Symbol Counter Beacon Timestamp Register LH-Byte


@@ 38,6 41,7 @@

; Register:    SCBTSRLL
; Description: Symbol Counter Beacon Timestamp Register LL-Byte

.equ           SCBTSRLL       = 0xE5
; Field:       SCBTSRLL
; Description: Symbol Counter Beacon Timestamp Register LL-Byte


@@ 48,6 52,7 @@

; Register:    SCCNTHH
; Description: Symbol Counter Register HH-Byte

.equ           SCCNTHH       = 0xE4
; Field:       SCCNTHH
; Description: Symbol Counter Register HH-Byte


@@ 58,6 63,7 @@

; Register:    SCCNTHL
; Description: Symbol Counter Register HL-Byte

.equ           SCCNTHL       = 0xE3
; Field:       SCCNTHL
; Description: Symbol Counter Register HL-Byte


@@ 68,6 74,7 @@

; Register:    SCCNTLH
; Description: Symbol Counter Register LH-Byte

.equ           SCCNTLH       = 0xE2
; Field:       SCCNTLH
; Description: Symbol Counter Register LH-Byte


@@ 78,6 85,7 @@

; Register:    SCCNTLL
; Description: Symbol Counter Register LL-Byte

.equ           SCCNTLL       = 0xE1
; Field:       SCCNTLL
; Description: Symbol Counter Register LL-Byte


@@ 88,6 96,7 @@

; Register:    SCCR0
; Description: Symbol Counter Control Register 0

.equ           SCCR0       = 0xDC
; Field:       SCCMP
; Description: Symbol Counter Compare Unit 3 Mode select


@@ 123,6 132,7 @@

; Register:    SCCR1
; Description: Symbol Counter Control Register 1

.equ           SCCR1       = 0xDD
; Field:       SCENBO
; Description: Backoff Slot Counter enable


@@ 138,6 148,7 @@

; Register:    SCIRQM
; Description: Symbol Counter Interrupt Mask Register

.equ           SCIRQM       = 0xDF
; Field:       IRQMCP
; Description: Symbol Counter Compare Match 3 IRQ enable


@@ 164,6 175,7 @@

; Register:    SCIRQS
; Description: Symbol Counter Interrupt Status Register

.equ           SCIRQS       = 0xE0
; Field:       IRQSCP
; Description: Compare Unit 3 Compare Match IRQ


@@ 190,6 202,7 @@

; Register:    SCOCR1HH
; Description: Symbol Counter Output Compare Register 1 HH-Byte

.equ           SCOCR1HH       = 0xF8
; Field:       SCOCR1HH
; Description: Symbol Counter Output Compare Register 1 HH-Byte


@@ 200,6 213,7 @@

; Register:    SCOCR1HL
; Description: Symbol Counter Output Compare Register 1 HL-Byte

.equ           SCOCR1HL       = 0xF7
; Field:       SCOCR1HL
; Description: Symbol Counter Output Compare Register 1 HL-Byte


@@ 210,6 224,7 @@

; Register:    SCOCR1LH
; Description: Symbol Counter Output Compare Register 1 LH-Byte

.equ           SCOCR1LH       = 0xF6
; Field:       SCOCR1LH
; Description: Symbol Counter Output Compare Register 1 LH-Byte


@@ 220,6 235,7 @@

; Register:    SCOCR1LL
; Description: Symbol Counter Output Compare Register 1 LL-Byte

.equ           SCOCR1LL       = 0xF5
; Field:       SCOCR1LL
; Description: Symbol Counter Output Compare Register 1 LL-Byte


@@ 230,6 246,7 @@

; Register:    SCOCR2HH
; Description: Symbol Counter Output Compare Register 2 HH-Byte

.equ           SCOCR2HH       = 0xF4
; Field:       SCOCR2HH
; Description: Symbol Counter Output Compare Register 2 HH-Byte


@@ 240,6 257,7 @@

; Register:    SCOCR2HL
; Description: Symbol Counter Output Compare Register 2 HL-Byte

.equ           SCOCR2HL       = 0xF3
; Field:       SCOCR2HL
; Description: Symbol Counter Output Compare Register 2 HL-Byte


@@ 250,6 268,7 @@

; Register:    SCOCR2LH
; Description: Symbol Counter Output Compare Register 2 LH-Byte

.equ           SCOCR2LH       = 0xF2
; Field:       SCOCR2LH
; Description: Symbol Counter Output Compare Register 2 LH-Byte


@@ 260,6 279,7 @@

; Register:    SCOCR2LL
; Description: Symbol Counter Output Compare Register 2 LL-Byte

.equ           SCOCR2LL       = 0xF1
; Field:       SCOCR2LL
; Description: Symbol Counter Output Compare Register 2 LL-Byte


@@ 270,6 290,7 @@

; Register:    SCOCR3HH
; Description: Symbol Counter Output Compare Register 3 HH-Byte

.equ           SCOCR3HH       = 0xF0
; Field:       SCOCR3HH
; Description: Symbol Counter Output Compare Register 3 HH-Byte


@@ 280,6 301,7 @@

; Register:    SCOCR3HL
; Description: Symbol Counter Output Compare Register 3 HL-Byte

.equ           SCOCR3HL       = 0xEF
; Field:       SCOCR3HL
; Description: Symbol Counter Output Compare Register 3 HL-Byte


@@ 290,6 312,7 @@

; Register:    SCOCR3LH
; Description: Symbol Counter Output Compare Register 3 LH-Byte

.equ           SCOCR3LH       = 0xEE
; Field:       SCOCR3LH
; Description: Symbol Counter Output Compare Register 3 LH-Byte


@@ 300,6 323,7 @@

; Register:    SCOCR3LL
; Description: Symbol Counter Output Compare Register 3 LL-Byte

.equ           SCOCR3LL       = 0xED
; Field:       SCOCR3LL
; Description: Symbol Counter Output Compare Register 3 LL-Byte


@@ 310,6 334,7 @@

; Register:    SCSR
; Description: Symbol Counter Status Register

.equ           SCSR       = 0xDE
; Field:       SCBSY
; Description: Symbol Counter busy


@@ 325,6 350,7 @@

; Register:    SCTSRHH
; Description: Symbol Counter Frame Timestamp Register HH-Byte

.equ           SCTSRHH       = 0xEC
; Field:       SCTSRHH
; Description: Symbol Counter Frame Timestamp Register HH-Byte


@@ 335,6 361,7 @@

; Register:    SCTSRHL
; Description: Symbol Counter Frame Timestamp Register HL-Byte

.equ           SCTSRHL       = 0xEB
; Field:       SCTSRHL
; Description: Symbol Counter Frame Timestamp Register HL-Byte


@@ 345,6 372,7 @@

; Register:    SCTSRLH
; Description: Symbol Counter Frame Timestamp Register LH-Byte

.equ           SCTSRLH       = 0xEA
; Field:       SCTSRLH
; Description: Symbol Counter Frame Timestamp Register LH-Byte


@@ 355,6 383,7 @@

; Register:    SCTSRLL
; Description: Symbol Counter Frame Timestamp Register LL-Byte

.equ           SCTSRLL       = 0xE9
; Field:       SCTSRLL
; Description: Symbol Counter Frame Timestamp Register LL-Byte

M atmega128rfa1/tc0.asm => atmega128rfa1/tc0.asm +9 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; TC0 peripheral register map assembly header for ATmega128RFA1
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    GTCCR
; Description: General Timer/Counter Control Register

.equ           GTCCR       = 0x43
; Field:       PSRSYNC
; Description: Prescaler Reset for Synchronous Timer/Counters


@@ 33,14 34,17 @@

; Register:    OCR0A
; Description: Timer/Counter0 Output Compare Register

.equ           OCR0A       = 0x47

; Register:    OCR0B
; Description: Timer/Counter0 Output Compare Register B

.equ           OCR0B       = 0x48

; Register:    TCCR0A
; Description: Timer/Counter0 Control Register A

.equ           TCCR0A       = 0x44
; Field:       WGM0
; Description: Waveform Generation Mode


@@ 84,6 88,7 @@

; Register:    TCCR0B
; Description: Timer/Counter0 Control Register B

.equ           TCCR0B       = 0x45
; Field:       CS0
; Description: Clock Select


@@ 124,10 129,12 @@

; Register:    TCNT0
; Description: Timer/Counter0 Register

.equ           TCNT0       = 0x46

; Register:    TIFR0
; Description: Timer/Counter0 Interrupt Flag Register

.equ           TIFR0       = 0x35
; Field:       TOV0
; Description: Timer/Counter0 Overflow Flag


@@ 153,6 160,7 @@

; Register:    TIMSK0
; Description: Timer/Counter0 Interrupt Mask Register

.equ           TIMSK0       = 0x6E
; Field:       TOIE0
; Description: Timer/Counter0 Overflow Interrupt Enable

M atmega128rfa1/tc1.asm => atmega128rfa1/tc1.asm +11 -1
@@ 2,28 2,33 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; TC1 peripheral register map assembly header for ATmega128RFA1
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    ICR1
; Description: Timer/Counter1 Input Capture Register  Bytes

.equ           ICR1       = 0x86

; Register:    OCR1A
; Description: Timer/Counter1 Output Compare Register A  Bytes

.equ           OCR1A       = 0x88

; Register:    OCR1B
; Description: Timer/Counter1 Output Compare Register B  Bytes

.equ           OCR1B       = 0x8A

; Register:    OCR1C
; Description: Timer/Counter1 Output Compare Register C  Bytes

.equ           OCR1C       = 0x8C

; Register:    TCCR1A
; Description: Timer/Counter1 Control Register A

.equ           TCCR1A       = 0x80
; Field:       WGM1
; Description: Waveform Generation Mode


@@ 72,6 77,7 @@

; Register:    TCCR1B
; Description: Timer/Counter1 Control Register B

.equ           TCCR1B       = 0x81
; Field:       CS1
; Description: Clock Select


@@ 117,6 123,7 @@

; Register:    TCCR1C
; Description: Timer/Counter1 Control Register C

.equ           TCCR1C       = 0x82
; Field:       RES
; Description: Reserved


@@ 142,10 149,12 @@

; Register:    TCNT1
; Description: Timer/Counter1  Bytes

.equ           TCNT1       = 0x84

; Register:    TIFR1
; Description: Timer/Counter1 Interrupt Flag Register

.equ           TIFR1       = 0x36
; Field:       TOV1
; Description: Timer/Counter1 Overflow Flag


@@ 175,6 184,7 @@

; Register:    TIMSK1
; Description: Timer/Counter1 Interrupt Mask Register

.equ           TIMSK1       = 0x6F
; Field:       TOIE1
; Description: Timer/Counter1 Overflow Interrupt Enable

M atmega128rfa1/tc2.asm => atmega128rfa1/tc2.asm +10 -1
@@ 2,12 2,13 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; TC2 peripheral register map assembly header for ATmega128RFA1
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    ASSR
; Description: Asynchronous Status Register

.equ           ASSR       = 0xB6
; Field:       TCR2BUB
; Description: Timer/Counter2 Control Register B Update Busy


@@ 52,6 53,7 @@

; Register:    GTCCR
; Description: General Timer Counter Control register

.equ           GTCCR       = 0x43
; Field:       PSRASY
; Description: Prescaler Reset Timer/Counter2


@@ 66,14 68,17 @@

; Register:    OCR2A
; Description: Timer/Counter2 Output Compare Register A

.equ           OCR2A       = 0xB3

; Register:    OCR2B
; Description: Timer/Counter2 Output Compare Register B

.equ           OCR2B       = 0xB4

; Register:    TCCR2A
; Description: Timer/Counter2 Control Register A

.equ           TCCR2A       = 0xB0
; Field:       WGM2
; Description: Waveform Generation Mode


@@ 117,6 122,7 @@

; Register:    TCCR2B
; Description: Timer/Counter2 Control Register B

.equ           TCCR2B       = 0xB1
; Field:       CS2
; Description: Clock Select


@@ 157,10 163,12 @@

; Register:    TCNT2
; Description: Timer/Counter2

.equ           TCNT2       = 0xB2

; Register:    TIFR2
; Description: Timer/Counter Interrupt Flag Register

.equ           TIFR2       = 0x37
; Field:       TOV2
; Description: Timer/Counter2 Overflow Flag


@@ 186,6 194,7 @@

; Register:    TIMSK2
; Description: Timer/Counter Interrupt Mask register

.equ           TIMSK2       = 0x70
; Field:       TOIE2
; Description: Timer/Counter2 Overflow Interrupt Enable

M atmega128rfa1/tc3.asm => atmega128rfa1/tc3.asm +11 -1
@@ 2,28 2,33 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; TC3 peripheral register map assembly header for ATmega128RFA1
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    ICR3
; Description: Timer/Counter3 Input Capture Register  Bytes

.equ           ICR3       = 0x96

; Register:    OCR3A
; Description: Timer/Counter3 Output Compare Register A  Bytes

.equ           OCR3A       = 0x98

; Register:    OCR3B
; Description: Timer/Counter3 Output Compare Register B  Bytes

.equ           OCR3B       = 0x9A

; Register:    OCR3C
; Description: Timer/Counter3 Output Compare Register C  Bytes

.equ           OCR3C       = 0x9C

; Register:    TCCR3A
; Description: Timer/Counter3 Control Register A

.equ           TCCR3A       = 0x90
; Field:       WGM3
; Description: Waveform Generation Mode


@@ 72,6 77,7 @@

; Register:    TCCR3B
; Description: Timer/Counter3 Control Register B

.equ           TCCR3B       = 0x91
; Field:       CS3
; Description: Clock Select


@@ 117,6 123,7 @@

; Register:    TCCR3C
; Description: Timer/Counter3 Control Register C

.equ           TCCR3C       = 0x92
; Field:       RES
; Description: Reserved


@@ 142,10 149,12 @@

; Register:    TCNT3
; Description: Timer/Counter3  Bytes

.equ           TCNT3       = 0x94

; Register:    TIFR3
; Description: Timer/Counter3 Interrupt Flag Register

.equ           TIFR3       = 0x38
; Field:       TOV3
; Description: Timer/Counter3 Overflow Flag


@@ 175,6 184,7 @@

; Register:    TIMSK3
; Description: Timer/Counter3 Interrupt Mask Register

.equ           TIMSK3       = 0x71
; Field:       TOIE3
; Description: Timer/Counter3 Overflow Interrupt Enable

M atmega128rfa1/tc4.asm => atmega128rfa1/tc4.asm +11 -1
@@ 2,28 2,33 @@
; Copyright (c) 2022 Kalyan Sriram <coder.kalyan@gmail.com>
;
; TC4 peripheral register map assembly header for ATmega128RFA1
; Generated on 2022-09-17 00:33:29
; Generated on 2022-09-17 17:11:36

; REGISTER DEFINITIONS

; Register:    ICR4