This repository is where I store code which is incomplete, broken, abandoned, or is generally below my normal standard of work. Some of it may be here because I lost interest in the project, because I decided it was too difficult, or simply because I didn't have time to polish it.
I have made this open for public access under an open source license in case others might find snippets useful, or wish to learn from pitfalls I may have encountered while trying to solve a problem.
In general, don't expect things here to be functional or particularly good.
This section contains projects that I started, but never finished, generally before the given project was mature enough to have it's own repository or web page.
I lost interest in this project because I could not figure out how to catch
ButtonRelease events, meaning that "click and drag" could not be implemented.
This is an obvious problem, as one would expect to be able to hold down the
mouse and move it around for this type of simulation.
Most of the scaffolding is in place, but the physics and collision logic has not been started yet, nor has any kind of control scheme.
Compile the code with
egg sand.c, and run with
Quick Ugly And Dirty Photo manager
I at one point started to implement a photo management library, with the intent of eventually building a GUI on top of it. I didn't know much about GUI development at the time, and thus couldn't figure out where to start with respect to building the GUI. As a result, the project was dropped.
The project contains a standard
setup.py file that may be used with
Unified Register Memory Architecture
In fall of 2018, I began work on a RISC architecture for high-performance symbol processing, intended for use on FPGAs. The key novelty of URMA was the lack of a memory hierarchy; it used a segmented relocatable register file -- different groups of registers could be offset by varying amounts to "look at" different regions of memory. A mostly complete assembler and simulator were written in C, and I had planned to eventually write a Verilog implementation, with the intent of using the SRAM blocks on a Stratix V FPGA to implement single-cycle flat memory access.
Upon further research and consideration, I determined that URMA would not ultimately be useful for high-performance computing, as the amount of SRAM resources even on high end modern FPGAs is insufficient to act as the entirety of addressable memory for a many-core implementation. Utilizing off-chip memory would not have permitted single-cycle memory access at a sufficiently high clock frequency to be useful.
Consequentially, the project has been abandoned, as it would not seem to be a fruitful line of research.
My attempt as a freshmen to write a CHIP-8 emulator in Python. It was never finished, as I got bored with the project. The name "pickle8" was a reference to an inside joke.