@@ 132,15 132,12 @@ fairly memory efficient.
# Future Work
* Better disassemble could be useful, especially with respect to load and
* Better disassembly could be useful, especially with respect to load and
store, and handling of non-canonical no-ops.
* A mode could be added to allow streaming instructions directly into memory,
rather than having to `poke` them in one at a time.
* A simple assembler could be added, allowing `riscv.awk` to be used as a
complete RISC-V toolchain.
* A `break` directive could be added, which halts the simulation on some
condition and implies a `dump` so it can later be resumed.