2 files changed, 15 insertions(+), 4 deletions(-)

M rv32.asm
M rv32s.asm

@@ 211,9 211,6 @@
 	sub  {rd: register}, {rs1: register}, {rs2: register} => asm { insn/R 0b0100000, {rs2}, {rs1}, 0b000, {rd}, 0b0110011 }
 	sra  {rd: register}, {rs1: register}, {rs2: register} => asm { insn/R 0b0100000, {rs2}, {rs1}, 0b101, {rd}, 0b0110011 }
 
-	mret => asm { insn/R 0b0011000, x2, x0, 0b000, x0, 0b1110011 }
-	sret => asm { insn/R 0b0001000, x2, x0, 0b000, x0, 0b1110011 }
-
 	;
 	; I encoding.
 	;

@@ 7,6 7,20 @@
 
 #ruledef rv32s
 {
-	wfi => le(0b0001000_00101_00000_000_00000_1110011)
+	mret => asm { insn/R 0b0011000, x2, x0, 0b000, x0, 0b1110011 }
+	sret => asm { insn/R 0b0001000, x2, x0, 0b000, x0, 0b1110011 }
+	uret => asm { insn/R 0b0000000, x2, x0, 0b000, x0, 0b1110011 }
+	wfi  => asm { insn/R 0b0001000, x5, x0, 0b000, x0, 0b1110011 }
+
+	sfence.vma {rs1: register}, {rs2: register} =>
+		asm { insn/R 0b0001001, {rs2}, {rs1}, 0b000, x0, 0b1110011 }
+	hfence.bvma {rs1: register}, {rs2: register} =>
+		asm { insn/R 0b0010001, {rs2}, {rs1}, 0b000, x0, 0b1110011 }
+	hfence.gvma {rs1: register}, {rs2: register} =>
+		asm { insn/R 0b1010001, {rs1}, {rs1}, 0b000, x0, 0b1110011 }
 }
 
+#ruledef rv32s_pseudo
+{
+	sfence.vma => asm { sfence.vma x0, x0 }
+}